Hi Nico,
Sorry for this late report. I am still fiddling with the coreboot code to
setup the SMM_BWP bit you suggested but with not much progress.
Beside the SMM_BWP, I followed your recommendation and was able to
successfully turn on the PR0 & FLOCKDN protections. I can confirm these by
running chipsec against the compiled image.
[chipsec_main@Controller_locked.txt]
I think I am fine at the moment and am somehow confident to put my X1
Carbon onto the internet. I will further explore coreboot codes for
additional flash memory write protections on my own.
I just want to express my gratitude for your help and towards the people
who make this project even possible and freely available to the whole
world, Thank you!!
My warmest regards,
Alan
---------- Forwarded message ---------
From: Alan K.L. Mok <alanm...@gmail.com>
Date: Sat, Jun 6, 2020 at 5:35 PM
Subject: Fwd: [coreboot] Anyway to change BIOSWE, BLE, SMM_BWP & PR0-5
protection bits?
To: <nic...@gmx.de>, <coreboot@coreboot.org>
Hello Nico,
Just a quick update that the platform I rely on (Debian 11 testing live)
for Coreboot compilation messed up itself after package updates and my
progress is retarded.
[Debian.jpg]
I had some readings on the PRx registers and now I understand that those
are registers accepting base, limit & range of address in memory to protect
from read/write and is provided and enforced by the SPI controller. I
completely agree with you that the protection bits I asked in my previous
email are not effective security measures since SMM code is privileged
enough to freely change those bits anytime and as you mentioned there is
presently not yet any secure SMM implementation (I think that the UEFI spec
makes everyones' life more difficult.....).
I will report back in next week on the menu makeconfig options you
mentioned in your previous email.
Thanks for your help,
Alan
---------- Forwarded message ---------
From: Alan K.L. Mok <alanm...@gmail.com>
Date: Sun, May 31, 2020 at 11:56 PM
Subject: Re: [coreboot] Anyway to change BIOSWE, BLE, SMM_BWP & PR0-5
protection bits?
To: Nico Huber <nic...@gmx.de>
Cc: <coreboot@coreboot.org>
Hello Nico,
Thank you very much for your reply, it is informative and helpful!
I will read more regarding the PRx registers and try to compile with the
menuconfig options you mentioned. Will also scrutinize the southbridge C
code and see if I can comprehend it. I will report back again within the
next few days.
Hope this email finds you are having a wonderful day,
Alan
On Sun, May 31, 2020 at 6:01 PM Nico Huber <nic...@gmx.de> wrote:
> Hello Alan,
>
> On 31.05.20 06:20, Alan K.L. Mok wrote:
> > 1. Can anyone please tell let me know how can I achieve the captioned
> > objectives? I looked into ifdtool & uefitool but found nothing related to
> > my goal. I also tried the "lock ME/TXE" option during make menuconfig but
> > Intel chipsec is still reporting the captioned bits not set on my
> > Coreboot-flashed X1 Carbon
>
> this option sets access permissions in the Flash Descriptor (IFD). They
> act like the PR0-5 registers but on top of them.
>
> The default settings (only valid ones as by Intel for production
> machines) will write-protect the IFD, read- and write-protect the
> ME region.
>
> > 2. Is it correct to say that once the PR0-5 bits are set and Coreboot
> > flashed into the machine, the values of the PR registers will be
> configured
> > accordingly after machine boot up (when OS is having control)?
>
> I'm not sure if I follow. Why do you call PR0-5 bits? those are
> registers that may or may not be filled with a flash range to
> protect. It is the host firmware's (coreboot's) responsibility
> to write these registers. But what values are to be written is
> up to you.
>
> Chipsec is a nice tool to check what things are configured and how.
> But the user still has to know how these things work. Otherwise they
> might make wrong assumptions about security. One good example is the
> FLOCKDN (flash lockdown) bit. When it's set, one cannot change the
> flash controller's configuration (including PR0-5 ranges) anymore
> until the next reboot. But it doesn't tell you if the locked confi-
> guration is secure, only that it can't be changed.
>
> > BIOSWE, BLE, SMM_BWP & PR0-5 protection bits
>
> BIOSWE, BLE, and SMM_BWP shift the blame from the OS to SMM (which is
> supposed to be controlled by the firmware). However, to my knowledge,
> nobody has yet achieved a secure SMM implementation. So many people
> ignore this. And IMHO, any good security concept shouldn't treat SMM
> more privileged than the OS.
>
> If you want to set these bits anyway, have a look at your south-
> bridge's code (src/southbridge/intel/bd82x6x/lpc.c), around
> pch_disable_smm_only_flashing(). This function clears SMM_BWP,
> I guess.
>
> The PR0-5 ranges can protect your flash efficiently, AFAIK. Not even
> SMM should be able to get around these. If you just want to write
> protect your whole flash chip (you won't be able to flash internally
> anymore), have a look at "Boot media protection mechanism" in the
> "Security" config menu. If set to "Lock boot media using the con-
> troller", it should use one of the PR0-5 ranges.
>
> FLOCKDN should be set when "Lock down chipset in coreboot" ("Chipset"
> menu) is enabled.
>
> Hope that helps,
> Nico
>
[39m################################################################
## ##
## CHIPSEC: Platform Hardware Security Assessment Framework ##
## ##
################################################################[0m
[39m[CHIPSEC] Version 1.5.1[0m
[39m[CHIPSEC] Arguments: [0m
[39m[0m
[39m****** Chipsec Linux Kernel module is licensed under GPL 2.0[0m
[39m[CHIPSEC] API mode: using CHIPSEC kernel module API[0m
[39m[CHIPSEC] OS : Linux 5.6.0-2-amd64 #1 SMP Debian 5.6.14-1
(2020-05-23) x86_64[0m
[39m[CHIPSEC] Python : 3.8.3 (64-bit)[0m
[39m[CHIPSEC] Helper : LinuxHelper
(/home/user/Downloads/chipsec-1.5.1/chipsec/helper/linux/chipsec.ko)[0m
[39m[CHIPSEC] Platform: Mobile 3rd Generation Core Processor (Ivy Bridge CPU /
Panther Point PCH)
[CHIPSEC] VID: 8086
[CHIPSEC] DID: 0154
[CHIPSEC] RID: 09[0m
[39m[CHIPSEC] PCH : Default PCH
[CHIPSEC] VID: FFFF
[CHIPSEC] DID: FFFF
[CHIPSEC] RID: FF[0m
[39m [0m
[39m[*] loading common modules from "./chipsec/modules/common" ..[0m
[39m[+] loaded chipsec.modules.common.bios_kbrd_buffer[0m
[39m[+] loaded chipsec.modules.common.bios_smi[0m
[39m[+] loaded chipsec.modules.common.bios_ts[0m
[39m[+] loaded chipsec.modules.common.bios_wp[0m
[39m[+] loaded chipsec.modules.common.cpu.cpu_info[0m
[39m[+] loaded chipsec.modules.common.cpu.ia_untrusted[0m
[39m[+] loaded chipsec.modules.common.cpu.spectre_v2[0m
[39m[+] loaded chipsec.modules.common.ia32cfg[0m
[39m[+] loaded chipsec.modules.common.me_mfg_mode[0m
[39m[+] loaded chipsec.modules.common.memlock[0m
[39m[+] loaded chipsec.modules.common.rtclock[0m
[39m[+] loaded chipsec.modules.common.secureboot.variables[0m
[39m[+] loaded chipsec.modules.common.sgx_check[0m
[39m[+] loaded chipsec.modules.common.smm[0m
[39m[+] loaded chipsec.modules.common.smrr[0m
[39m[+] loaded chipsec.modules.common.spd_wd[0m
[39m[+] loaded chipsec.modules.common.spi_access[0m
[39m[+] loaded chipsec.modules.common.spi_desc[0m
[39m[+] loaded chipsec.modules.common.spi_fdopss[0m
[39m[+] loaded chipsec.modules.common.spi_lock[0m
[39m[+] loaded chipsec.modules.common.uefi.access_uefispec[0m
[39m[+] loaded chipsec.modules.common.uefi.s3bootscript[0m
[39m[*] loading platform specific modules from "./chipsec/modules/ivb" ..[0m
[39m[+] loaded chipsec.modules.common.bios_kbrd_buffer[0m
[39m[+] loaded chipsec.modules.common.bios_smi[0m
[39m[+] loaded chipsec.modules.common.bios_ts[0m
[39m[+] loaded chipsec.modules.common.bios_wp[0m
[39m[+] loaded chipsec.modules.common.cpu.cpu_info[0m
[39m[+] loaded chipsec.modules.common.cpu.ia_untrusted[0m
[39m[+] loaded chipsec.modules.common.cpu.spectre_v2[0m
[39m[+] loaded chipsec.modules.common.ia32cfg[0m
[39m[+] loaded chipsec.modules.common.me_mfg_mode[0m
[39m[+] loaded chipsec.modules.common.memlock[0m
[39m[+] loaded chipsec.modules.common.rtclock[0m
[39m[+] loaded chipsec.modules.common.secureboot.variables[0m
[39m[+] loaded chipsec.modules.common.sgx_check[0m
[39m[+] loaded chipsec.modules.common.smm[0m
[39m[+] loaded chipsec.modules.common.smrr[0m
[39m[+] loaded chipsec.modules.common.spd_wd[0m
[39m[+] loaded chipsec.modules.common.spi_access[0m
[39m[+] loaded chipsec.modules.common.spi_desc[0m
[39m[+] loaded chipsec.modules.common.spi_fdopss[0m
[39m[+] loaded chipsec.modules.common.spi_lock[0m
[39m[+] loaded chipsec.modules.common.uefi.access_uefispec[0m
[39m[+] loaded chipsec.modules.common.uefi.s3bootscript[0m
[39m[*] loading modules from "./chipsec/modules" ..[0m
[39m[+] loaded chipsec.modules.common.bios_kbrd_buffer[0m
[39m[+] loaded chipsec.modules.common.bios_smi[0m
[39m[+] loaded chipsec.modules.common.bios_ts[0m
[39m[+] loaded chipsec.modules.common.bios_wp[0m
[39m[+] loaded chipsec.modules.common.cpu.cpu_info[0m
[39m[+] loaded chipsec.modules.common.cpu.ia_untrusted[0m
[39m[+] loaded chipsec.modules.common.cpu.spectre_v2[0m
[39m[+] loaded chipsec.modules.common.ia32cfg[0m
[39m[+] loaded chipsec.modules.common.me_mfg_mode[0m
[39m[+] loaded chipsec.modules.common.memlock[0m
[39m[+] loaded chipsec.modules.common.rtclock[0m
[39m[+] loaded chipsec.modules.common.secureboot.variables[0m
[39m[+] loaded chipsec.modules.common.sgx_check[0m
[39m[+] loaded chipsec.modules.common.smm[0m
[39m[+] loaded chipsec.modules.common.smrr[0m
[39m[+] loaded chipsec.modules.common.spd_wd[0m
[39m[+] loaded chipsec.modules.common.spi_access[0m
[39m[+] loaded chipsec.modules.common.spi_desc[0m
[39m[+] loaded chipsec.modules.common.spi_fdopss[0m
[39m[+] loaded chipsec.modules.common.spi_lock[0m
[39m[+] loaded chipsec.modules.common.uefi.access_uefispec[0m
[39m[+] loaded chipsec.modules.common.uefi.s3bootscript[0m
[39m[+] loaded chipsec.modules.debugenabled[0m
[39m[+] loaded chipsec.modules.memconfig[0m
[39m[+] loaded chipsec.modules.remap[0m
[39m[+] loaded chipsec.modules.smm_dma[0m
[39m[*] running loaded modules ..[0m
[39m
[*] running module: chipsec.modules.common.bios_kbrd_buffer[0m
[34m[x][
=======================================================================
[x][ Module: Pre-boot Passwords in the BIOS Keyboard Buffer
[x][ =======================================================================[0m
[39m[*] Keyboard buffer head pointer = 0x24 (at 0x41A), tail pointer = 0x24
(at 0x41C)[0m
[39m[*] Keyboard buffer contents (at 0x41E):[0m
[39m1B 01 32 03 0D 1C 00 00 00 00 00 00 00 00 00 00 | 2
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | [0m
[31m[-] Keyboard buffer tail points inside the buffer (= 0x24)[0m
[31mERROR: Exception occurred during
chipsec.modules.common.bios_kbrd_buffer.run(): 'Unknown format code 'd' for
object of type 'float''[0m
[39m
[*] running module: chipsec.modules.common.bios_smi[0m
[34m[x][
=======================================================================
[x][ Module: SMI Events Configuration
[x][ =======================================================================[0m
[31m[-] SMM BIOS region write protection has not been enabled (SMM_BWP is not
used)
[0m
[39m[*] Checking SMI enables..[0m
[39m Global SMI enable: 1[0m
[39m TCO SMI enable : 1[0m
[32m[+] All required SMI events are enabled[0m
[39m[0m
[39m[*] Checking SMI configuration locks..[0m
[32m[+] TCO SMI configuration is locked (TCO SMI Lock)[0m
[32m[+] SMI events global configuration is locked (SMI Lock)[0m
[39m[0m
[32m[+] PASSED: All required SMI sources seem to be enabled and locked[0m
[39m
[*] running module: chipsec.modules.common.bios_ts[0m
[34m[x][
=======================================================================
[x][ Module: BIOS Interface Lock (including Top Swap Mode)
[x][ =======================================================================[0m
[39m[*] BiosInterfaceLockDown (BILD) control = 1[0m
[39m[*] BIOS Top Swap mode is disabled (TSS = 0)[0m
[39m[*] RTC TopSwap control (TS) = 0[0m
[32m[+] PASSED: BIOS Interface is locked (including Top Swap Mode)[0m
[39m
[*] running module: chipsec.modules.common.bios_wp[0m
[34m[x][
=======================================================================
[x][ Module: BIOS Region Write Protection
[x][ =======================================================================[0m
[39m[*] BC = 0x09 << BIOS Control (b:d.f 00:31.0 + 0xDC)
[00] BIOSWE = 1 << BIOS Write Enable
[01] BLE = 0 << BIOS Lock Enable
[02] SRC = 2 << SPI Read Configuration
[04] TSS = 0 << Top Swap Status
[05] SMM_BWP = 0 << SMM BIOS Write Protection [0m
[31m[-] BIOS region write protection is disabled![0m
[39m
[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF[0m
[39mSPI Protected Ranges[0m
[39m------------------------------------------------------------[0m
[39mPRx (offset) | Value | Base | Limit | WP? | RP?[0m
[39m------------------------------------------------------------[0m
[39mPR0 (74) | 8BFF8000 | 00000000 | 00BFFFFF | 1 | 1 [0m
[39mPR1 (78) | 00000000 | 00000000 | 00000000 | 0 | 0 [0m
[39mPR2 (7C) | 00000000 | 00000000 | 00000000 | 0 | 0 [0m
[39mPR3 (80) | 00000000 | 00000000 | 00000000 | 0 | 0 [0m
[39mPR4 (84) | 00000000 | 00000000 | 00000000 | 0 | 0 [0m
[39m[0m
[32m[+] PASSED: SPI Protected Ranges are configured to write protect BIOS[0m
[39m
[*] running module: chipsec.modules.common.cpu.cpu_info[0m
[34m[x][
=======================================================================
[x][ Module: Current Processor Information:
[x][ =======================================================================[0m
[39m[*] Thread 0000[0m
[39m[*] Processor: Intel(R) Core(TM) i5-3337U CPU @ 1.80GHz[0m
[39m[*] Family: 06 Model: 3A Stepping: 9[0m
[39m[*] Microcode: 00000021[0m
[39m[*][0m
[39m[*] Thread 0001[0m
[39m[*] Processor: Intel(R) Core(TM) i5-3337U CPU @ 1.80GHz[0m
[39m[*] Family: 06 Model: 3A Stepping: 9[0m
[39m[*] Microcode: 00000021[0m
[39m[*][0m
[39m[*] Thread 0002[0m
[39m[*] Processor: Intel(R) Core(TM) i5-3337U CPU @ 1.80GHz[0m
[39m[*] Family: 06 Model: 3A Stepping: 9[0m
[39m[*] Microcode: 00000021[0m
[39m[*][0m
[39m[*] Thread 0003[0m
[39m[*] Processor: Intel(R) Core(TM) i5-3337U CPU @ 1.80GHz[0m
[39m[*] Family: 06 Model: 3A Stepping: 9[0m
[39m[*] Microcode: 00000021[0m
[39m[*][0m
[32m[#] INFORMATION: Processor information displayed[0m
[39m
[*] running module: chipsec.modules.common.cpu.ia_untrusted[0m
[39mSkipping module chipsec.modules.common.cpu.ia_untrusted since it is not
supported in this platform[0m
[39m
[*] running module: chipsec.modules.common.cpu.spectre_v2[0m
[34m[x][
=======================================================================
[x][ Module: Checks for Branch Target Injection / Spectre v2 (CVE-2017-5715)
[x][ =======================================================================[0m
[39m[*] CPUID.7H:EDX[26] = 1 Indirect Branch Restricted Speculation (IBRS) &
Predictor Barrier (IBPB)[0m
[39m[*] CPUID.7H:EDX[27] = 1 Single Thread Indirect Branch Predictors
(STIBP)[0m
[39m[*] CPUID.7H:EDX[29] = 0 IA32_ARCH_CAPABILITIES[0m
[32m[+] CPU supports IBRS and IBPB[0m
[32m[+] CPU supports STIBP[0m
[31m[-] CPU doesn't support enhanced IBRS[0m
[33m[!] WARNING: CPU supports mitigation (IBRS) but doesn't support enhanced
IBRS[0m
[31m[!] OS may be using software based mitigation (eg. retpoline)[0m
[39m
[*] running module: chipsec.modules.common.ia32cfg[0m
[34m[x][
=======================================================================
[x][ Module: IA32 Feature Control Lock
[x][ =======================================================================[0m
[39m[*] Verifying IA32_Feature_Control MSR is locked on all logical CPUs..[0m
[39m[*] cpu0: IA32_Feature_Control Lock = 1[0m
[39m[*] cpu1: IA32_Feature_Control Lock = 1[0m
[39m[*] cpu2: IA32_Feature_Control Lock = 1[0m
[39m[*] cpu3: IA32_Feature_Control Lock = 1[0m
[32m[+] PASSED: IA32_FEATURE_CONTROL MSR is locked on all logical CPUs[0m
[39m
[*] running module: chipsec.modules.common.me_mfg_mode[0m
[34m[x][
=======================================================================
[x][ Module: ME Manufacturing Mode
[x][ =======================================================================[0m
[31m[-] FAILED: ME is in Manufacturing Mode[0m
[39m
[*] running module: chipsec.modules.common.memlock[0m
[34m[x][
=======================================================================
[x][ Module: Check MSR_LT_LOCK_MEMORY
[x][ =======================================================================[0m
[39m[X] Checking MSR_LT_LOCK_MEMORY status[0m
[39m[*] cpu0: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m
[39m[*] cpu1: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m
[39m[*] cpu2: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m
[39m[*] cpu3: MSR_LT_LOCK_MEMORY[LT_LOCK] = 1[0m
[32m[+] PASSED: Check have successfully passed[0m
[39m
[*] running module: chipsec.modules.common.rtclock[0m
[34m[x][
=======================================================================
[x][ Module: Protected RTC memory locations
[x][ =======================================================================[0m
[39m[*] RC = 0x00000004 << RTC Configuration (RCBA + 0x3400)
[02] UE = 1 << Upper 128 Byte Enable
[03] LL = 0 << Lower 128 Byte Lock
[04] UL = 0 << Upper 128 Byte Lock [0m
[31m[-] Protected bytes (0x38-0x3F) in low 128-byte bank of RTC memory are not
locked[0m
[31m[-] Protected bytes (0x38-0x3F) in high 128-byte bank of RTC memory are
not locked[0m
[33m[!] WARNING: Protected locations in RTC memory are accessible (BIOS may
not be using them)[0m
[39m
[*] running module: chipsec.modules.common.secureboot.variables[0m
[33m[*] NOT IMPLEMENTED: OS does not support UEFI Runtime API[0m
[39mSkipping module chipsec.modules.common.secureboot.variables since it is
not supported in this platform[0m
[39m
[*] running module: chipsec.modules.common.sgx_check[0m
[39mSkipping module chipsec.modules.common.sgx_check since it is not supported
in this platform[0m
[39m
[*] running module: chipsec.modules.common.smm[0m
[34m[x][
=======================================================================
[x][ Module: Compatible SMM memory (SMRAM) Protection
[x][ =======================================================================[0m
[39m[*] PCI0.0.0_SMRAMC = 0x1A << System Management RAM Control (b:d.f 00:00.0
+ 0x88)
[00] C_BASE_SEG = 2 << SMRAM Base Segment = 010b
[03] G_SMRAME = 1 << SMRAM Enabled
[04] D_LCK = 1 << SMRAM Locked
[05] D_CLS = 0 << SMRAM Closed
[06] D_OPEN = 0 << SMRAM Open [0m
[39m[*] Compatible SMRAM is enabled[0m
[32m[+] PASSED: Compatible SMRAM is locked down[0m
[39m
[*] running module: chipsec.modules.common.smrr[0m
[34m[x][
=======================================================================
[x][ Module: CPU SMM Cache Poisoning / System Management Range Registers
[x][ =======================================================================[0m
[32m[+] OK. SMRR range protection is supported[0m
[39m[0m
[39m[*] Checking SMRR range base programming..[0m
[39m[*] IA32_SMRR_PHYSBASE = 0xC0000006 << SMRR Base Address MSR (MSR 0x1F2)
[00] Type = 6 << SMRR memory type
[12] PhysBase = C0000 << SMRR physical base address [0m
[39m[*] SMRR range base: 0x00000000C0000000[0m
[39m[*] SMRR range memory type is Writeback (WB)[0m
[32m[+] OK so far. SMRR range base is programmed[0m
[39m[0m
[39m[*] Checking SMRR range mask programming..[0m
[39m[*] IA32_SMRR_PHYSMASK = 0xFF800800 << SMRR Range Mask MSR (MSR 0x1F3)
[11] Valid = 1 << SMRR valid
[12] PhysMask = FF800 << SMRR address range mask [0m
[39m[*] SMRR range mask: 0x00000000FF800000[0m
[32m[+] OK so far. SMRR range is enabled[0m
[39m[0m
[39m[*] Verifying that SMRR range base & mask are the same on all logical
CPUs..[0m
[39m[CPU0] SMRR_PHYSBASE = 00000000C0000006, SMRR_PHYSMASK =
00000000FF800800[0m
[39m[CPU1] SMRR_PHYSBASE = 00000000C0000006, SMRR_PHYSMASK =
00000000FF800800[0m
[39m[CPU2] SMRR_PHYSBASE = 00000000C0000006, SMRR_PHYSMASK =
00000000FF800800[0m
[39m[CPU3] SMRR_PHYSBASE = 00000000C0000006, SMRR_PHYSMASK =
00000000FF800800[0m
[32m[+] OK so far. SMRR range base/mask match on all logical CPUs[0m
[39m[*] Trying to read memory at SMRR base 0xC0000000..[0m
[32m[+] PASSED: SMRR reads are blocked in non-SMM mode[0m
[39m[0m
[32m[+] PASSED: SMRR protection against cache attack is properly configured[0m
[39m
[*] running module: chipsec.modules.common.spd_wd[0m
[34m[x][
=======================================================================
[x][ Module: SPD Write Disable
[x][ =======================================================================[0m
[31m[-] FAILED: SPD Write Disable is not set and SPDs were detected[0m
[39m
[*] running module: chipsec.modules.common.spi_access[0m
[34m[x][
=======================================================================
[x][ Module: SPI Flash Region Access Control
[x][ =======================================================================[0m
[39mSPI Flash Region Access Permissions[0m
[39m------------------------------------------------------------[0m
[39m[0m
[39mBIOS Region Write Access Grant (00):[0m
[39m FREG0_FLASHD: 0[0m
[39m FREG1_BIOS : 0[0m
[39m FREG2_ME : 0[0m
[39m FREG3_GBE : 0[0m
[39m FREG4_PD : 0[0m
[39m FREG5 : 0[0m
[39m FREG6 : 0[0m
[39mBIOS Region Read Access Grant (00):[0m
[39m FREG0_FLASHD: 0[0m
[39m FREG1_BIOS : 0[0m
[39m FREG2_ME : 0[0m
[39m FREG3_GBE : 0[0m
[39m FREG4_PD : 0[0m
[39m FREG5 : 0[0m
[39m FREG6 : 0[0m
[39mBIOS Region Write Access (AA):[0m
[39m FREG0_FLASHD: 0[0m
[39m FREG1_BIOS : 1[0m
[39m FREG2_ME : 0[0m
[39m FREG3_GBE : 1[0m
[39m FREG4_PD : 0[0m
[39m FREG5 : 1[0m
[39m FREG6 : 0[0m
[39mBIOS Region Read Access (B0B):[0m
[39m FREG0_FLASHD: 1[0m
[39m FREG1_BIOS : 1[0m
[39m FREG2_ME : 0[0m
[39m FREG3_GBE : 1[0m
[39m FREG4_PD : 0[0m
[39m FREG5 : 0[0m
[39m FREG6 : 0[0m
[33m[!] WARNING: Software has write access to GBe region in SPI flash[0m
[33m[!] WARNING: Certain SPI flash regions are writeable by software[0m
[39m
[*] running module: chipsec.modules.common.spi_desc[0m
[34m[x][
=======================================================================
[x][ Module: SPI Flash Region Access Control
[x][ =======================================================================[0m
[39m[*] FRAP = 0x00000A0B << SPI Flash Regions Access Permissions Register
(SPIBAR + 0x50)
[00] BRRA = B << BIOS Region Read Access
[08] BRWA = A << BIOS Region Write Access
[16] BMRAG = 0 << BIOS Master Read Access Grant
[24] BMWAG = 0 << BIOS Master Write Access Grant [0m
[39m[*] Software access to SPI flash regions: read = 0x0B, write = 0x0A[0m
[39m[0m
[32m[+] PASSED: SPI flash permissions prevent SW from writing to flash
descriptor[0m
[39m
[*] running module: chipsec.modules.common.spi_fdopss[0m
[34m[x][
=======================================================================
[x][ Module: SPI Flash Descriptor Security Override Pin-Strap
[x][ =======================================================================[0m
[39m[*] HSFS = 0xE008 << Hardware Sequencing Flash Status Register (SPIBAR +
0x4)
[00] FDONE = 0 << Flash Cycle Done
[01] FCERR = 0 << Flash Cycle Error
[02] AEL = 0 << Access Error Log
[03] BERASE = 1 << Block/Sector Erase Size
[05] SCIP = 0 << SPI cycle in progress
[13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status
[14] FDV = 1 << Flash Descriptor Valid
[15] FLOCKDN = 1 << Flash Configuration Lock-Down [0m
[32m[+] PASSED: SPI Flash Descriptor Security Override is disabled[0m
[39m
[*] running module: chipsec.modules.common.spi_lock[0m
[34m[x][
=======================================================================
[x][ Module: SPI Flash Controller Configuration Locks
[x][ =======================================================================[0m
[39m[*] HSFS = 0xE008 << Hardware Sequencing Flash Status Register (SPIBAR +
0x4)
[00] FDONE = 0 << Flash Cycle Done
[01] FCERR = 0 << Flash Cycle Error
[02] AEL = 0 << Access Error Log
[03] BERASE = 1 << Block/Sector Erase Size
[05] SCIP = 0 << SPI cycle in progress
[13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status
[14] FDV = 1 << Flash Descriptor Valid
[15] FLOCKDN = 1 << Flash Configuration Lock-Down [0m
[32m[+] SPI Flash Controller configuration is locked[0m
[32m[+] PASSED: SPI Flash Controller locked correctly.[0m
[39m
[*] running module: chipsec.modules.common.uefi.access_uefispec[0m
[33m[*] NOT IMPLEMENTED: OS does not support UEFI Runtime API[0m
[39mSkipping module chipsec.modules.common.uefi.access_uefispec since it is
not supported in this platform[0m
[39m
[*] running module: chipsec.modules.common.uefi.s3bootscript[0m
[33m[*] NOT IMPLEMENTED: OS does not support UEFI Runtime API[0m
[39mSkipping module chipsec.modules.common.uefi.s3bootscript since it is not
supported in this platform[0m
[39m
[*] running module: chipsec.modules.debugenabled[0m
[33m[*] NOT IMPLEMENTED: CPU Debug features are not supported on this
platform[0m
[39mSkipping module chipsec.modules.debugenabled since it is not supported in
this platform[0m
[39m
[*] running module: chipsec.modules.memconfig[0m
[34m[x][
=======================================================================
[x][ Module: Host Bridge Memory Map Locks
[x][ =======================================================================[0m
[39m[*][0m
[39m[*] Checking register lock state:[0m
[32m[+] PCI0.0.0_BDSM = 0x C0A00001 - LOCKED - Base of
Graphics Stolen Memory[0m
[32m[+] PCI0.0.0_BGSM = 0x C0800001 - LOCKED - Base of GTT
Stolen Memory[0m
[32m[+] PCI0.0.0_DPR = 0x C0000001 - LOCKED - DMA Protected
Range[0m
[32m[+] PCI0.0.0_GGC = 0x 209 - LOCKED - Graphics
Control[0m
[32m[+] PCI0.0.0_MESEG_MASK = 0x 400 - LOCKED - Manageability
Engine Limit Address Register[0m
[32m[+] PCI0.0.0_PAVPC = 0x 4 - LOCKED - PAVP
Configuration[0m
[32m[+] PCI0.0.0_REMAPBASE = 0x 100000001 - LOCKED - Memory Remap
Base Address[0m
[32m[+] PCI0.0.0_REMAPLIMIT = 0x 13D500001 - LOCKED - Memory Remap
Limit Address[0m
[32m[+] PCI0.0.0_TOLUD = 0x C2A00001 - LOCKED - Top of Low
Usable DRAM[0m
[32m[+] PCI0.0.0_TOM = 0x 100000001 - LOCKED - Top of
Memory[0m
[32m[+] PCI0.0.0_TOUUD = 0x 13D600001 - LOCKED - Top of Upper
Usable DRAM[0m
[32m[+] PCI0.0.0_TSEGMB = 0x C0000001 - LOCKED - TSEG Memory
Base[0m
[39m[*][0m
[32m[+] PASSED: All memory map registers seem to be locked down[0m
[39m
[*] running module: chipsec.modules.remap[0m
[34m[x][
=======================================================================
[x][ Module: Memory Remapping Configuration
[x][ =======================================================================[0m
[39m[*] Registers:[0m
[39m[*] TOUUD : 0x000000013D600001[0m
[39m[*] REMAPLIMIT: 0x000000013D500001[0m
[39m[*] REMAPBASE : 0x0000000100000001[0m
[39m[*] TOLUD : 0xC2A00001[0m
[39m[*] TSEGMB : 0xC0000001
[0m
[39m[*] Memory Map:[0m
[39m[*] Top Of Upper Memory: 0x000000013D600000[0m
[39m[*] Remap Limit Address: 0x000000013D5FFFFF[0m
[39m[*] Remap Base Address : 0x0000000100000000[0m
[39m[*] 4GB : 0x0000000100000000[0m
[39m[*] Top Of Low Memory : 0x00000000C2A00000[0m
[39m[*] TSEG (SMRAM) Base : 0x00000000C0000000
[0m
[39m[*] checking memory remap configuration..[0m
[39m[*] Memory Remap is enabled[0m
[32m[+] Remap window configuration is correct: REMAPBASE <= REMAPLIMIT <
TOUUD[0m
[32m[+] All addresses are 1MB aligned[0m
[39m[*] checking if memory remap configuration is locked..[0m
[32m[+] TOUUD is locked[0m
[32m[+] TOLUD is locked[0m
[32m[+] REMAPBASE and REMAPLIMIT are locked[0m
[32m[+] PASSED: Memory Remap is configured correctly and locked[0m
[39m
[*] running module: chipsec.modules.smm_dma[0m
[34m[x][
=======================================================================
[x][ Module: SMM TSEG Range Configuration Check
[x][ =======================================================================[0m
[39m[*] TSEG : 0x00000000C0000000 - 0x00000000C07FFFFF (size =
0x00800000)[0m
[39m[*] SMRR range: 0x00000000C0000000 - 0x00000000C07FFFFF (size = 0x00800000)
[0m
[39m[*] checking TSEG range configuration..[0m
[32m[+] TSEG range covers entire SMRAM[0m
[32m[+] TSEG range is locked[0m
[32m[+] PASSED: TSEG is properly configured. SMRAM is protected from DMA
attacks[0m
[39m
[CHIPSEC] *************************** SUMMARY ***************************[0m
[39m[CHIPSEC] Time elapsed 0.059[0m
[39m[CHIPSEC] Modules total 26[0m
[39m[CHIPSEC] Modules failed to run 1:[0m
[31mERROR: chipsec.modules.common.bios_kbrd_buffer[0m
[39m[CHIPSEC] Modules passed 13:[0m
[32m[+] PASSED: chipsec.modules.common.bios_smi[0m
[32m[+] PASSED: chipsec.modules.common.bios_ts[0m
[32m[+] PASSED: chipsec.modules.common.bios_wp[0m
[32m[+] PASSED: chipsec.modules.common.ia32cfg[0m
[32m[+] PASSED: chipsec.modules.common.memlock[0m
[32m[+] PASSED: chipsec.modules.common.smm[0m
[32m[+] PASSED: chipsec.modules.common.smrr[0m
[32m[+] PASSED: chipsec.modules.common.spi_desc[0m
[32m[+] PASSED: chipsec.modules.common.spi_fdopss[0m
[32m[+] PASSED: chipsec.modules.common.spi_lock[0m
[32m[+] PASSED: chipsec.modules.memconfig[0m
[32m[+] PASSED: chipsec.modules.remap[0m
[32m[+] PASSED: chipsec.modules.smm_dma[0m
[39m[CHIPSEC] Modules information 1:[0m
[32m[#] INFORMATION: chipsec.modules.common.cpu.cpu_info[0m
[39m[CHIPSEC] Modules failed 2:[0m
[31m[-] FAILED: chipsec.modules.common.me_mfg_mode[0m
[31m[-] FAILED: chipsec.modules.common.spd_wd[0m
[39m[CHIPSEC] Modules with warnings 3:[0m
[33m[!] WARNING: chipsec.modules.common.cpu.spectre_v2[0m
[33m[!] WARNING: chipsec.modules.common.rtclock[0m
[33m[!] WARNING: chipsec.modules.common.spi_access[0m
[39m[CHIPSEC] Modules not implemented 3:[0m
[33m[*] NOT IMPLEMENTED: chipsec.modules.common.secureboot.variables[0m
[33m[*] NOT IMPLEMENTED: chipsec.modules.common.uefi.access_uefispec[0m
[33m[*] NOT IMPLEMENTED: chipsec.modules.common.uefi.s3bootscript[0m
[39m[CHIPSEC] Modules not applicable 3:[0m
[33m[*] NOT APPLICABLE: chipsec.modules.common.cpu.ia_untrusted[0m
[33m[*] NOT APPLICABLE: chipsec.modules.common.sgx_check[0m
[33m[*] NOT APPLICABLE: chipsec.modules.debugenabled[0m
[39m[CHIPSEC] Modules with exceptions 1:[0m
[31mERROR: chipsec.modules.common.bios_kbrd_buffer[0m
[39m[CHIPSEC]
*****************************************************************[0m
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