Hi, I have been following the typical approach of compiling Coreboot integrated with Inte FSP; SeaBIOS as payload, for my Minnowboard MAX dual ethernet board. On flashing, I couldn't reach at SeaBIOS shell.
I noticed that SPD EEPROM(U33) is not mounted in order to configure the DDR. I could flash and reach UEFI shell using below firmware images https://software.intel.com/content/www/us/en/develop/articles/minnowboard-maxturbot-uefi-firmware.html but couldn't succeed flashing coreboot with FSP. How to configure DDR following such a configuration? Regards, Derryl Tauro
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