Hi, Thanks for the information - it's more than I've had before. Maybe someone else can shed more light on the exact workings, but in the meantime I'll take a look at MMCONFIG.
Cheers, Rafael On Fri, Nov 27, 2020 at 10:45 AM Rudolf Marek <[email protected]> wrote: > Hi, > > On 25. 11. 20 20:26, Rafael Send wrote: > > Any ideas for what I could try here, or reasons why it might not (be > expected to) work? > > The extended PCI configuration space access requires a special memory > region (up 256MiB) which translate accesses to > the PCI configuration cycles. It is exported via ACPI table MMCONFIG. Each > 4K basically is one PCI/PCIe device > first is bus 0, device 0, fn 0 second is fn 1 etc etc. > > So, this information about this special area has to be somehow available > to your EFI shell. Sorry I don't know > how this works I could only give you this general overview. > > Some chipsets also support backdoor access to the extended PCIe config > space, by utilizing the reserved bits > in the 0xcf8 access I/O port to address the extra offsets. This is > non-standard chipset dependent feature > which is usually even off. > > Thanks, > Rudolf > >
_______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]

