Hi, I'm stuck at solving a problem on Intel platforms that might not be one after all.
Tests showed that a HyperThreading enabled core must not update microcodes on both threads at the same time, as the UCODE silicon is shared between those threads and one update might fail. However, doing so might not cause problems on devices newer than the Pentium 4 (as stated in some SDMs). Intel's SDM requires the use of semaphores to only update one thread of a core at once. In order to follow the microcode update flow described in Intel SDM I've moved some essential parts of coreboot's MP init code (aka SIPI vector) to C code [1]. While it makes it easier to maintain and reuse existing code (especially semaphores), it doesn't follow SDM to update microcode first no matter what. I'm not sure if all the work/changes are really necessary. The questions here are: * Do we care about Intel platforms supporting FIT? Those do update the microcode on all cores before executing the reset vector anyway and thus MP init won't update microcode at all. Following Intel SDM here is pointless. * Do we care about Intel platforms not supporting FIT (aka pre Haswell)? Those could update one core at time using a spinlock whenever HyperThreading is enabled. Assuming the limited amount of logical cores on those old platforms the additional boot delay might be very low. Another option would be to update microcode in parallel without a spinlock assuming that no Pentium 4 will ever run this code. Following Intel SDM here, given the low number of cores, won't give any significant speed up while adding complex code. * Do we care about Intel platforms supporting FIT not using FIT? Following Intel SDM here, assuming a high number of cores, will give significant speed up while adding complex code. * Should the SIPI vector in general be partially moved from assembly to C? This makes it easier to add features and reuse code, but compilers might generate unsupported code. To summarize: Instead of adding a bunch of code I'd prefer to serialize MP init microcode updates on non FIT and Hyper-Threading enabled CPUs only. 1: https://review.coreboot.org/q/topic:%22mpinit_cleanup%22+(status:open%20OR%20status:merged) Kind Regards, Patrick Rudolph B.Sc. Electrical Engineering System Firmware Developer 9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany Email: [email protected] Phone: +49 234 68 94 188 Sitz der Gesellschaft: Bochum Handelsregister: Amtsgericht Bochum, HRB 17519 Geschäftsführung: Sebastian Deutsch, Eray Basar Datenschutzhinweise nach Art. 13 DSGVO _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
