this code worked for me i am hyped
can we make something out of it ?
diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig
index 7cf80e0a91..5b5bfc66c5 100644
--- a/src/mainboard/protectli/vault_kbl/Kconfig
+++ b/src/mainboard/protectli/vault_kbl/Kconfig
@@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS
select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
select SOC_INTEL_KABYLAKE
select SPI_FLASH_MACRONIX
- select SUPERIO_ITE_IT8772F
+ select SUPERIO_ITE_IT8613E
select MAINBOARD_HAS_CRB_TPM
select HAVE_INTEL_PTT
select TPM2
diff --git a/src/mainboard/protectli/vault_kbl/bootblock.c b/src/mainboard/protectli/vault_kbl/bootblock.c
index a11b5fdc3b..fcc7f13cc2 100644
--- a/src/mainboard/protectli/vault_kbl/bootblock.c
+++ b/src/mainboard/protectli/vault_kbl/bootblock.c
@@ -1,16 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
-#include <superio/ite/it8772f/it8772f.h>
+#include <superio/ite/it8613e/it8613e.h>
#include <superio/ite/common/ite.h>
-#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
-#define UART_DEV PNP_DEV(0x2e, IT8772F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
+//#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1)
+#define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1)
+//#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
void bootblock_mainboard_early_init(void)
{
- ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24);
- ite_enable_3vsbsw(GPIO_DEV);
- ite_kill_watchdog(GPIO_DEV);
- ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
+ //ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24);
+ //ite_enable_3vsbsw(GPIO_DEV);
+ //ite_kill_watchdog(GPIO_DEV);
+ //ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
+
+
+ ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable K8 power seq */
+ ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */
+ ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
}
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index dc73f91478..b00269dcf7 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -246,26 +246,18 @@ chip soc/intel/skylake
device pci 1e.4 off end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 off end # SDCard
- device pci 1f.0 on
- chip superio/ite/it8772f
- register "peci_tmpin" = "3"
- register "tmpin1_mode" = "THERMAL_RESISTOR"
- register "tmpin2_mode" = "THERMAL_RESISTOR"
- # FAN2 available on fan header but unused
- device pnp 2e.0 off end # FDC
- device pnp 2e.1 on # Serial Port 1
+ device pci 1f.0 on # 8086 229c - LPC bridge
+ chip superio/ite/it8613e
+ device pnp 2e.0 off end
+ device pnp 2e.1 on # COM 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 2e.4 on # Environment Controller
- io 0x60 = 0xa40
- io 0x62 = 0xa30
- irq 0x70 = 9
- end
+ device pnp 2e.4 off end # Environment Controller
device pnp 2e.5 off end # Keyboard
device pnp 2e.6 off end # Mouse
device pnp 2e.7 off end # GPIO
- device pnp 2e.a off end # IR
+ device pnp 2e.a off end # CIR
end
end # LPC Interface
device pci 1f.1 on end # P2SB
_______________________________________________
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org
