Hello everyone, I would like to take part in the development of coreboot projects and become a GSoC 2022 contributor. I'm not a newbie in firmwares (I have experience with uefi, I'm familiar with bios). Now, to prepare myself, I study the coreboot documentation and source code.
I find "Libpayload based memtest payload" and "Fix POST code handling" projects interesting. But I need some tips. About the first one. To put it simply, the task is to study the memtest sources (memory checking mechanisms) and port it? And of course improve it, if possible. I have more questions about the last one projects: 1) Main goal is to make Kconfigs have effect on most platforms. For it we should maybe have deal with Kconfigs and replace to post_code(...) which refer to POST_IO and POST_IO_PORT. Right? 2) For example, in `arch/x86/tables.c`, line 81: post_code(0x9c); coreboot has no documentation and macro for POST code 0x9c. So, should I find out what it means and write it in the documentation and add a macro? 3) What does the task "Make use of all possible 255 values" mean? Does coreboot use all 255 values? I would appreciate any feedback. -- Joursoir _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
