# 2022-03-29 - coreboot UEFI working group
Next meeting: 2022-04-26
## Attendees:
Jay, Werner, Martin, Sheng, Ron, David
## Minutes:
* In the coreboot meeting last week, we discussed a proposal from Intel
to change the handoff mechanism to payloads [1]. After that
discussion, the decision was made to move further discussion of that
topic over to the UEFI working group meeting. There was another
meeting on Monday, March 28th where we got a much better understanding
of what’s going on and the reasons behind the proposal.
* Intel wants to look at modifying the payload handoff as a part of
their universal-scalable-firmware [2] initiative.
* The current payload handoff method has a number of flaws that
they’d like to fix, such as the address for stack being
hardcoded.
* This likely also gives coreboot an opportunity to address
other parts of the USF spec that cause issues or
incompatibilities for us.
* The coreboot project got involved when Sheng suggested to Intel
that it would be good to align the payload-handoff format with
other projects such as coreboot.
* Thanks Sheng!
* Using CBOR is the current proposal, but Intel was open to
discussing different formats than CBOR if anyone has a better
suggestion.
* If anyone is not familiar with CBOR, you can get more
information at cbor.io [3].
* In the coreboot meeting, it was suggested that we push to just use
coreboot tables as they’re already supported in a number of
payloads. This really isn’t practical however. Intel would need
to be able to modify the list of known cbmem IDs and they would
need to be able to change the description format to something
that’s more self-describing.
* The coreboot project can, however, encapsulate a CBOR-based
handoff-structure into cbmem, similar to what we currently do with
ACPI tables.
* Additionally Intel was willing to look at using CBOR structures as
input and output to the FSP, so we could get rid of both the UPDs
& HOBs.
* The coreboot community can help to drive this, and Intel has said
that they will send an email to the coreboot mailing list.
* Since this is a part of the Universal-Scalable-Firmware
initiative, it would be good to look that over for issues as well.
Currently, it’s very Intel oriented, and specifies that the FSP
will be used as the silicon initialization layer, which obviously
doesn’t work for non-x86 platforms.
* The details for the weekly meeting are below.
* Self Describing Blob discussion.
A copy of this meeting has been added to the coreboot calendar [4].
Biweekly on Monday, 4:00 – 5:00pm CET/CEST Berlin (Currently UTC+2)
Video call link: https://meet.google.com/gha-shza-wnw
Or dial: (DE) +49 30 300195187 PIN: 848 847 031#
More phone numbers: https://tel.meet/gha-shza-wnw?pin=2380921555764
Self Describing Blob discussion Meeting minutes [5].
* Sean Rhodes from StarLabs has worked to get all of the coreboot
related EDK2 patches submitted to their repo. These are still
currently in review.
[1]:
https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit#bookmark=id.om2nw7l8b4xe
[2]: https://universalscalablefirmware.github.io/documentation/
[3]: https://cbor.io/
[4]:
https://calendar.google.com/event?action=TEMPLATE&tmeid=NHVvZDRuYXZ2bjdtZTJjN2J1c3A2dGRsYmVfMjAyMjAzMjhUMTQwMDAwWiBxMDVtYzVsOTM5bHA3NDZlMGs3b2lidXFwb0Bn&tmsrc=q05mc5l939lp746e0k7oibuqpo%40group.calendar.google.com&scp=ALL
[5]:
https://docs.google.com/document/d/1IDQqr4cv8dQHa9faSxBc29xHSeKuXNTiMP3a3bLJClQ/edit
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