On 8.03.2023 21:09, baptx wrote:
> Ok, I missed the list email address since it was not in CC so I could not use
> the "reply all" feature.
> So if I understand correctly, we just need to set the value in FspmUpd.h by
> changing the code to something like "ActiveSmallCoreCount = 0;" before 
> building
> and flashing coreboot?

Exactly.


> Are there already some FSP parameters that we can change without reflashing? 
> For
> example like we can do to disable / enable Intel Management Engine using
> nvramtool
> (https://github.com/system76/firmware-open/blob/master/docs/intel-me.md
> <https://github.com/system76/firmware-open/blob/master/docs/intel-me.md>).

No, there aren't. Only hyperthreading and legacy 8254 timer is hooked to CMOS
NVRAM currently.

Best regards,
-- 
Michał Żygowski
Firmware Engineer
GPG: 6B5BA214D21FCEB2
https://3mdeb.com | @3mdeb_com

Attachment: OpenPGP_0x6B5BA214D21FCEB2.asc
Description: OpenPGP public key

Attachment: OpenPGP_signature
Description: OpenPGP digital signature

_______________________________________________
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

Reply via email to