Issue #508 has been updated by Yu-Ping Wu.
Arthur Heymans wrote in #note-3: > I don't understand the hardware however I tried to look at the soc code. > In soc/mediatek/common/pcie.c I see the following: > > write32p(table, mmio_res->cpu_addr | > PCIE_ATR_SIZE(__fls(mmio_res->size))); > > Correct me if I'm wrong but would this not only program the most significant > bit of the mmio region size? > Could it be that instead of a 48M window a 32M window is actually set up > which would break top down allocation? > Would it be worth trying to set a size of 64M or 32M? Yes, you're right. This will be fixed in https://review.coreboot.org/c/coreboot/+/78044. Thanks. ---------------------------------------- Bug #508: Dojo fails to boot from NVMe with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled https://ticket.coreboot.org/issues/508#change-1660 * Author: Yu-Ping Wu * Status: New * Priority: Normal * Assignee: Nico Huber * Target version: none * Start date: 2023-08-31 * Affected versions: 4.21 ---------------------------------------- Similar to #499, after https://review.coreboot.org/c/coreboot/+/75012, Dojo fails to boot. Disabling CONFIG_RESOURCE_ALLOCATION_TOP_DOWN fixes the problem. However I'm not sure how to fix it from MediaTek's PCIe functions or settings (for example mtk_pcie_domain_read_resources). ---Files-------------------------------- ap-bad.log (32.8 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
