Hello Hamish, welcome back!
Most (non-server) Intel SoCs are supported by coreboot, from ~Core 2 Duo up to PantherLake (which *should* be released at CES 2026 in two days, but can't say more than that). BayTrail and ApolloLake that you mentioned are fully supported, but don't have great documentation. They were used by Google in Chromebooks, so that should give you some ideas as to where to start. One thing you should keep in mind is that APL/GLK SoCs are a bit "cursed". They can boot from SPI... as well as eMMC (presumably they've been developed for automotive sector) and mFIT will nag you to fuse them with BootGuard (similar to BootROM verifying PBL with vendor's keys). All APL systems I've seen in the wild were fused (with the exception of Chromebooks), but it will not be a problem if you have signing keys. As for unbricking/developing: Currently the cheapest/best SPI flashers you can get your hands on is either a Raspberry Pi Pico, or CH347. They do however have a limitation of being 3.3V, so you will likely need to buy a 1.8V logic shifter as all APL systems I've seen in the wild used 1.8V SPI. (This is also mandatory for all mobile ZEN-based SoCs, I'm currently working on Framework 16 with Zen4 and all I/O on that SoC is 1.8V) As for recommendations, DediProg EM100 is the current "industry standard", but it's... not cheap. Last time I've checked it cost close to 1000EUR/piece. It has a Spartan Xilinx 6 FPGA inside (newer models likely have a Spartan 7) and supports both 1.8 and 3.3V SPI chips. Hope this helps! - elly On 04/01/2026 19:06, Hamish Guthrie wrote: > > Hello Coreboot community, > > After a rather long hiatus (my last commits to LinuxBIOS were in 2005) - my > work had moved me to PPC/MIPS and now mainly ARM architectures, so have been > using u-boot for many years. > > The company I work for has a large range of embedded devices, for which we > use a common platform for ARM devices, and we have completed a major re-work > on this platform to ensure RED and CRA compliance. I have been tasked with > migrating a range of industrial embedded x86 devices to our common platform, > to prepare these products for CRA compliance. There are many thousands of > these x86 devices in the field, using either Q7 or COM-Express modules with > various generations (Bay Trail, Apollo Lake and Elkhart Lake) of Intel > processors. > > My 2 concerns are boot speed and BIOS updates. Devices with Bay Trail and > Apollo Lake SoC's have customised BIOS's and it appears as though the BIOS > vendor simply forked their BIOS code in 2015 and no security updates have > been made at all - even though they have made modifications to these BIOS's > as recently as November 2025. Of course attempting to find real information > about this is impossible. > > I have been looking through the Coreboot documentation in a lot of detail in > preparation, but would like to ask for some friendly advice about de-bricking > these devices when I start trying to flash coreboot into them! All of these > modules have SO-8 SPI flash devices on them, and I assume a good SPI flash > programmer would be useful, I also guess for development that an SPI flash > emulator could be very useful. Could anyone provide me recommendations for > decent devices for this purpose? > > Hamish > > > _______________________________________________ > coreboot mailing list -- [email protected] > To unsubscribe send an email to [email protected] _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
