Issue #655 has been reported by Dawid Wrobel. ---------------------------------------- Bug #655: m920q fails to do_global_reset() after 25.06 https://ticket.coreboot.org/issues/655
* Author: Dawid Wrobel * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2026-06-30 * Affected versions: none * Affected hardware: m920q ---------------------------------------- I attempted to upgrade 25.06 to 26.06 and the system fails to reboot. Serial console shows: ``` [DEBUG] Starting cbfs_boot_device [INFO ] CBFS: Found 'fallback/payload' @0x186200 size 0x16f875 in mcache @0x89ced394 [DEBUG] Checking segment from ROM address 0xff91722c [DEBUG] Checking segment from ROM address 0xff917248 [DEBUG] Loading segment from ROM address 0xff91722c [DEBUG] code (compression=1) [DEBUG] New segment dstaddr 0x00800000 memsize 0xa00000 srcaddr 0xff917264 filesize 0x16f83d [DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000a00000 filesz: 0x000000000016f83d [DEBUG] using LZMA [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 12649673533 [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 13078746300 [DEBUG] Loading segment from ROM address 0xff917248 [DEBUG] Entry Point 0x00803ac5 [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 230 / 91 ms [INFO ] Timestamp - calling FspNotify(ReadyToBoot): 13124864519 [INFO ] Timestamp - returning from FspNotify(ReadyToBoot): 13157210020 [DEBUG] GLOBAL RESET! [INFO ] global_reset() called! [DEBUG] HECI: Global Reset(Type:1) Command [DEBUG] HECI: Global Reset success! ``` Everything seems just fine here, except the reset actually does *not* happen at this point, but it did with 25.06. This most likely has something to do with changes made `do_global_reset()` sometime after 25.06: ``` ~/coreboot-builder-scripts/m920q/build# git log 25.06..25.12 --oneline -- src/soc/intel/cannonlake/ src/mainboard/lenovo/m920q/ src/soc/intel/common/block/cse/ 7f93e2fe29 soc/intel/*: Add CFR option to enable/disable the Intel iGPU d5ea359347 soc/intel/**/cfr.h: Fix typo of "ACPI" in UI help text 84a4cdc6a5 soc/intel/*: Only skip PMC fallback on successful CSE reset 4f52ca6ba6 soc/intel/common/cse: Return usable error codes 50a59d4464 device: Add Kconfig to prepare for reworked verb table implementation fbc2d76ab3 soc/intel/*: Select 'DRAM_SUPPORT_DDRx' as appropriate da49da6c82 soc/intel: Add Arrow Lake-S/HX IDs 626c5364b8 tree: Use boolean for PcieRpSlotImplemented[] ``` and the candidate that stands out is `84a4cdc6a5`: ``` commit 84a4cdc6a533dc909a25fde25d99dca13ad2d28c Author: Sean Rhodes <[email protected]> Date: Sat Nov 29 20:41:03 2025 +0000 soc/intel/*: Only skip PMC fallback on successful CSE reset cse_request_global_reset() returns CSE_TX_RX_SUCCESS on success. Make do_global_reset() explicatly check for that, and fall back CF9 for any other value. Test=Disable and enable the Intel ME on starbook_mtl and verify the system actually resets, rather than hanging. Change-Id: I4c3fb7995bca8e7fe3793b9aee021e4004ace933 Signed-off-by: Sean Rhodes <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90273 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Matt DeVillier <[email protected]> diff --git a/src/soc/intel/alderlake/reset.c b/src/soc/intel/alderlake/reset.c index bc5815ac7a..3c13f6dfe5 100644 --- a/src/soc/intel/alderlake/reset.c +++ b/src/soc/intel/alderlake/reset.c @@ -8,7 +8,7 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (cse_request_global_reset()) + if (cse_request_global_reset() == CSE_TX_RX_SUCCESS) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index bc5815ac7a..3c13f6dfe5 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -8,7 +8,7 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (cse_request_global_reset()) + if (cse_request_global_reset() == CSE_TX_RX_SUCCESS) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/elkhartlake/reset.c b/src/soc/intel/elkhartlake/reset.c index bc5815ac7a..3c13f6dfe5 100644 (...) ``` and 4f52ca6ba6: ``` commit 4f52ca6ba666dbebc7cc4e299d7b49796ac297d8 Author: Sean Rhodes <[email protected]> Date: Sat Nov 29 20:37:06 2025 +0000 soc/intel/common/cse: Return usable error codes Currently, cse_request_reset() returns 0 if the reset type is unsupported or CSE isn’t ready. This is the same as CSE_TX_RX_SUCCESS, which makes failures impossible to detect. Return CSE_TX_ERR_INPUT or CSE_TX_ERR_CSE_NOT_READY respectively, so we can detect errors. Change-Id: Idede7342157901946ba62ba6fcda6f304a4a3fd0 Signed-off-by: Sean Rhodes <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90272 Reviewed-by: Jérémy Compostella <[email protected]> Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Matt DeVillier <[email protected]> diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 1f519312ce..d02bb85b37 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -737,12 +737,12 @@ static int cse_request_reset(enum rst_req_type rst_type) if (!(rst_type == GLOBAL_RESET || rst_type == CSE_RESET_ONLY)) { printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n"); - return 0; + return CSE_TX_ERR_INPUT; } if (!cse_is_global_reset_allowed() || !is_cse_enabled()) { printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); - return 0; + return CSE_TX_ERR_CSE_NOT_READY; } heci_reset(); (...) ``` -- You have received this notification because you have either subscribed to it, or are involved in it. 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