Issue #658 has been updated by Nicholas Chin.
Keith Hui wrote in #note-15: > Out of curiosity I downloaded the boardview for this board. This is a board > released in a time as we transition from DDR2 to DDR3, so it has slots for > BOTH. The slots, counting outwards from the CPU socket, are: > > DDR3 channel A (SPD index 0x50) > DDR2 channel A (SPD index 0x51) > DDR3 channel B (SPD index 0x52) > DDR2 channel B (SPD index 0x53) > > That means you only have one usable slot per channel. You can't use both DDR2 > and DDR3 together. I was chatting with Gabriel and `spd_map[0] = 0x50, spd_map[2] = 0x52` works for DDR3, while `spd_map[0] = 0x51, spd_map[2] = 0x53` works for DDR2. This suggests that the DDR2 and DDR3 slots are both connected to memory controller slot 1 in each channel, which is also supported by the board diagram (https://theretroweb.com/motherboards/s/asus-p5g41c-m). The diagram shows that they are both connected to A1 (channel A slot 1) and B1 (channel B slot 1) rather than something like A1, A2, B1, B2. This means there are multiple possible SPD indexes for each memory controller slot, which coreboot's raminit code doesn't currently support. I'm not sure what would be a good way to generalize handling these sorts of things for different situations. The P5QC seems to have DDR2 slots for both memory controller slots in both channels, as well as a DDR3 slot for first memory controller slot in each channel. The P5QL-EM also seems to be another unusual case. ---------------------------------------- Bug #658: asus p5g41c-m-lx pcie discovery of realtek 10ec:8168 https://ticket.coreboot.org/issues/658#change-2395 * Author: Gabriel Turlea * Status: New * Priority: Normal * Target version: none * Start date: 2026-07-14 ---------------------------------------- I have tried to port coreboot to asus-p5g41c-m-lx by using the existing pg541t-m-lx variant. Everything works great except I cannot get the onboard lan realtek 10ec:8168 to be detected by coreboot. The card shows up and works once linux boots. Adding some register values in the overridetree.cb seems to disable the card even in linux. Please let me know what supporting info I should provide. Thank you ---Files-------------------------------- p5g41c_m-lx_cbmem.log (53.5 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
