Hi despair.
On Coffee Lake the FSP-M parameter 'PlatformDebugConsent' needs to be
set to 2 (at least that is my experience with later Intel platforms). It
seems like the soc code does so depending on the Kconfig option
'CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT'. In addition, make sure to
enable 'SOC_INTEL_DEBUG_CONSENT' (which you should do anyway to make
'SOC_INTEL_COMMON_DEBUG_CONSENT' effective).
That is pretty much it what needs to be done on coreboot side.
On Elkhart Lake and Alder Lake I know that DCI works if you set the
debug consent in coreboot's Kconfig to 2 or 3, depending on how you
access DCI (yellow cable, DCI Dbc Adapter, ...)). And I cannot recall
that it has been changed so I am quite confident that it should be the
same for Coffee Lake as well.
In addition, are you confident that you enabled DCI in the descriptor
properly? If you have access to NDA docs, you might have access to FIT
tool from Intel as well. If yes, look around there how to properly
enable DCI. From recent platforms I know that one have to enable DCI
globally and then enable it for a given USB port. If you just enable one
of these options, DCI will not work.
Regards
Werner
-------- Original-Nachricht --------
Subject: Need guidance on enabling DCI debugging for ThinkPad T480 with
coreboot
Dear coreboot community,
My name is despair, and I am working on enabling DCI (Direct Connect
Interface) debugging on my ThinkPad T480. I have rebuilt coreboot
multiple times trying to get DCI working, but all attempts have failed
so far.
What I have tried:
· Compiled coreboot with various configurations (I can provide
my .config if needed).
· After compilation, I used ifdtool (as suggested in some mailing list
threads) to enable DCI in the flash descriptor.
· With the default settings, I found that the CPU could not be
suspended/paused properly.
· When I changed the DCI parameter to 1, I was able to suspend the CPU,
but then I attempted to perform DMA memory reads through the PCH
(southbridge) without suspending the CPU, following Intel's guidance (I
have access to NDA documentation). However, during debugging, I could
not locate the SoC TAP chain – only the DCI-side device appears.
My specific questions:
1. What are the correct steps to compile a coreboot firmware for the
T480 that fully enables DCI debugging from scratch?
2. Are there any specific Kconfig options, patches, or runtime
parameters that I must set to make both CPU suspension and TAP chain
discovery work?
3. Could the issue be related to the flash descriptor, ME firmware, or
the debug firmware (e.g., Intel FSP) that I am using?
I understand that DCI debugging is a complex topic, and I would really
appreciate any pointers or known working configurations. Please let me
know if you need my .config, build logs, or more details about my exact
procedure.
Thank you in advance for your help!
Best regards,
despair
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