Hi
Hope you are doing well !!
My name is *Harish Karnala* and I am a
*technical
recruiter* with *United Software group*. One of my clients in the *San
Jose, CA* area currently has FPGA Engineer that they are looking to fill.
Here are the details on the role.
*JD: *
Role
FPGA Engineer
Mandatory Technical Skills
*MUST*
* - to have skill set *1. Hands on Experience with semi-custom ASIC
development
2.
*Should have design and Development experience with Xilinx/Altera FPGA/CPLD
*3.
*Should have at least 5 yrs of dedicated exp. with FPGA based design &
development. *4. Should have hands on experience with *verilog/VHDL/System
Verilog* languages
5.
*Should have experience with test bench development, functional testing and
verification. *6. Should be able to understand Hardware design and develop
the FPGA code.
7.
*Experience with USB, Ethernet, I2C & SPI interfaces are mandatory *8.
*Good Debugging skills *9.
*Good understanding of network concepts and packet based protocols,
hardware implementation of FFT, sourcing coding techniques. *10. Must have
experience with VHDL/Verilog to develop firmware
11. Understanding of perl, TCL and shell scripts
12. Expertise in writing test benches (SV based) and test planning.
13. *Should have worked on both module and system level verification*.
14. Should have worked on regressions, coverage.
15.* Strong Digital signal processing algorithms (FFT/Filter etc).*
12. Expertise in writing test benches (SV based) and test planning.
*MUST* - to have skill set
1. Hands on Experience with semi custom ASIC development
2.
*Should have design and Development experience with Xilinx/Altera FPGA/CPLD
*3.
*Should have atleast 5 yrs of dedicated exp. with FPGA based design &
development. *4. Should have hands on experience with verilog/VHDL/System
Verilog languages
5.
*Should have experience with test bench development, functional testing and
verification. *6. Should be able to understand Hardware design and develop
the FPGA code.
7.
*Experience with USB, Ethernet, I2C & SPI interfaces are mandatory *8.
*Good Debugging skills *9.
*Good understanding of network concepts and packet based protocols,
hardware implementation of FFT, sourcing coding techniques. *10. Must have
experiene with VHDL/Verilog to develop firmware
11. Understanding of perl, TCL and shell scripts
13. *Should have worked on both module and system level verification*.
14. Should have worked on regressions, coverage.
15.* Strong Digital signal processing algorithms (FFT/Filter etc).*
Desirable Technical Skills
*GOOD*
* - to have skill set *1. Design and Verification of the FPGA/CPLD code -
Xilinx/Altera
2. Should be able to understand hardware design documents and drive the
FPGA based designs independently
3. Good understanding of Digital signal processing concepts *GOOD*
* - to have skill set *1. Design and Verification of the FPGA/CPLD code -
Xilinx/Altera
2. Should be able to understand hardware design documents and drive the
FPGA based designs independently
3. Good understanding of Digital signal processing concepts
Desirable Functional Skills
FPGA/CPLD - Xilinx/Altera, Xilinx ISE, Verilog/VHDL, System Verilog
Total Experience Required
5-9 yrs
Work Location
San Jose, CA, USA
Duration
1yr
Harish Karnala
United Software Group Inc..
565 Metro Place South. Suite # 110
<https://maps.google.com/?q=565+Metro+Place+South.+Suite+%23+110++Dublin,+OH+43017&entry=gmail&source=g>
Dublin, OH 43017
<https://maps.google.com/?q=565+Metro+Place+South.+Suite+%23+110++Dublin,+OH+43017&entry=gmail&source=g>
Direct Number : +1 614-408 1549
Board Number : 614-495-9222 EXT. 622
Fax: 1-866-764-1148
[email protected]
Hangouts: [email protected]
www.usgrpinc.com
--
You received this message because you are subscribed to the Google Groups
"CorptoCorp" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
To post to this group, send email to [email protected].
Visit this group at https://groups.google.com/group/corptocorp.
For more options, visit https://groups.google.com/d/optout.