The answer you are looking for is Karnaugh logic maps. This will produce an unoptimized set of gate logic that represents say S-boxes or E-tables.
>From there you can find smaller gate logic compliments that produce the same logic map. Christopher Abad and I researched this heavily a few years ago regarding DES S-Boxes. He has provided his gatelogic reduction code on his site, http://www.the-mathclub.net. I can send you my generic gate logic optimizer if you'd like. I have one for standard (&,|,^,~), mmx/sse2 (&,|,^,~,&~), and vhdl/verilog (&,|,^,~,~&,~|,~^). Anyhow, best of luck. -Patrick Stach --------------------------------------------------------------------- The Cryptography Mailing List Unsubscribe by sending "unsubscribe cryptography" to [EMAIL PROTECTED]
