On Fri, Nov 29, 2013 at 11:22:29AM +0100, Joachim Strömbergson wrote: > What I was trying to say is that Havege running on MCUs (AVR, AVR32, > PIC, PIC32, ARM Cortex M0 etc) where instructions in general takes the > same number of cycles to execute and where caches are few (few levels), > have simple or even no replacement policy (it is done by SW control), > the assumptions in Havege is not really present. And that this change in > physical setup _should_ affect the variance measured. But again, I > haven't tested it yet.
howdy, i tried out the default haveged code found under: http://www.irisa.fr/caps/projects/hipsor/misc.php#measure on an arm cortex m3 stm32f2xx and streamed the results over uart and plotted them here: https://www.ctrlc.hu/~stef/stm32f2x-jitter.png prefetch, data and instruction cache where enabled. cheers,s -- pgp: https://www.ctrlc.hu/~stef/stef.gpg pgp fp: FD52 DABD 5224 7F9C 63C6 3C12 FC97 D29F CA05 57EF otr fp: https://www.ctrlc.hu/~stef/otr.txt _______________________________________________ cryptography mailing list [email protected] http://lists.randombit.net/mailman/listinfo/cryptography
