On 5/8/15, coderman <coder...@gmail.com> wrote: > ... > has there been consideration of a processor instruction for hardware > implementation resistant to timing attacks?
to answer my own question, SIMD like NEON on ARM cores appears to be plenty sufficient, if you code the rest accommodating. e.g. performing independent operations together: https://cryptojedi.org/peter/data/ches-20120911.pdf where independent operations together is independent data single instruction. best regards, _______________________________________________ cryptography mailing list cryptography@randombit.net http://lists.randombit.net/mailman/listinfo/cryptography
