Hi Everyone,

This is a big FYI...

The test script has been showing a small issue when using a minimally 
featured cpu:

c++ -DNDEBUG -g2 -O2 -msse -msse2 -fPIC -march=native -pipe -c sha.cpp
ERROR: failed to generate sha1rnds4 instruction
ERROR: failed to generate sha1nexte instruction
ERROR: failed to generate sha1msg1 instruction
ERROR: failed to generate sha1msg2 instruction
ERROR: failed to generate sha256rnds2 instruction
ERROR: failed to generate sha256msg1 instruction
ERROR: failed to generate sha256msg2 instruction

This use case is the distro's, where they build without --march=native and 
then distribute the library to users with a variety of machines.

We used to have code that handled the use case. It was removed at 
http://github.com/weidai11/cryptopp/commit/fb6a11ff08b9. The code was 
removed for two reasons. First, it caused a few minor problems, like 
http://github.com/weidai11/cryptopp/issues/53 due to C++11 constexpr (for 
example, an IMM needs a CONSTEXPR or template parameter, not a function 
parameter). Second, GCC Bug 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57202 stated intrinsics would 
always be available is GCC version 5 and above.

With the fb6a11ff08b9 removal and the 57202 bug, I thought the new use 
cases would be: (1) GCC 5 users and above would get the intrinsics, and (2) 
GCC 4 and below would get CXX by default. GCC 4.8 and 4.9 users could 
install an updated compiler from backports, and move from (2) into (1). It 
would simplify the code and side step the 53 bug. It seemed like a good 
trade-off simplicity and performance while side stepping bugs.

It turns out 57202 did not enable intrinsics all the time. Additionally, it 
only enables intrinsics for IA32 (and not other platforms like ARM). I 
advised Wei incorrectly, so I got the OK to remove the code. Arg...

I want to start adding the code back incrementally. I'm going to start with 
SHA since its the immediate painpoint. But we need to do it for AEN-NI, 
PCLMUL, SSE4, and some SSSE3. And we need to do it with ARM, but ARM's a 
little trickier because of some assembler goodness. For the ARM assembler 
issue see https://sourceware.org/ml/binutils/2017-04/msg00171.html.

Jeff

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