On Apr 16, 2008, at 6:40 AM, John Baldwin wrote:
On Monday 14 April 2008 04:34:45 pm Marcel Moolenaar wrote:
marcel 2008-04-14 20:34:45 UTC
FreeBSD src repository
Modified files:
sys/ia64/ia64 sapic.c
Log:
Revision 1.9 changes the delivery mode from the magic constant 0
(i.e. fixed delivery) to SAPIC_DELMODE_LOWPRI. While the commit
log doesn't mention the change in behaviour, it is believed to be
deliberate. In the last 5.5 years this hasn't been a problem. Nor
do I think did it make any difference, but who knows. However, I
do know that it break SMP support for Montecito-based machines.
Switch back to fixed-CPU delivery so that SMP works again. This
gives me some time to look more closely at the problem, as well
as make sure the I-cache validation as it's implemented currently
is sufficient in SMP configurations...
Intel is deprecating the LOWPRI delivery mode on x86 CPUs with
x2APIC, so I
think it is probably best to switch to using FIXED mode on ia64 as
well (x86
has used fixed mode since the new APIC code came in due to LOWPRI
being
effectively useless on P4 CPUs).
That's good to know. If LOWPRI has the same destiny in Itanium
chipsets as it has in Pentium chipsets, then I might as well
avoid the hassle of getting it to work. Though, I do like it
when all CPUs share in the interrupt handling. Maybe I can do
that more easily with MSI (which I still need to implement :-)
Thanks,
--
Marcel Moolenaar
[EMAIL PROTECTED]
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