Repository : ssh://darcs.haskell.org//srv/darcs/ghc On branch : master
http://hackage.haskell.org/trac/ghc/changeset/6fe4f8d560bedfd21289a1a9f9360a371b3a5246 >--------------------------------------------------------------- commit 6fe4f8d560bedfd21289a1a9f9360a371b3a5246 Author: Ian Lynagh <[email protected]> Date: Tue May 31 16:56:40 2011 +0100 Whitespace only in nativeGen/RegAlloc/Linear/Base.hs >--------------------------------------------------------------- compiler/nativeGen/RegAlloc/Linear/Base.hs | 130 ++++++++++++++-------------- 1 files changed, 65 insertions(+), 65 deletions(-) diff --git a/compiler/nativeGen/RegAlloc/Linear/Base.hs b/compiler/nativeGen/RegAlloc/Linear/Base.hs index 9fd090c..087ab9c 100644 --- a/compiler/nativeGen/RegAlloc/Linear/Base.hs +++ b/compiler/nativeGen/RegAlloc/Linear/Base.hs @@ -2,18 +2,18 @@ -- | Put common type definitions here to break recursive module dependencies. module RegAlloc.Linear.Base ( - BlockAssignment, + BlockAssignment, - Loc(..), - regsOfLoc, + Loc(..), + regsOfLoc, - -- for stats - SpillReason(..), - RegAllocStats(..), + -- for stats + SpillReason(..), + RegAllocStats(..), - -- the allocator monad - RA_State(..), - RegM(..) + -- the allocator monad + RA_State(..), + RegM(..) ) where @@ -30,40 +30,40 @@ import UniqSupply -- | Used to store the register assignment on entry to a basic block. --- We use this to handle join points, where multiple branch instructions --- target a particular label. We have to insert fixup code to make --- the register assignments from the different sources match up. +-- We use this to handle join points, where multiple branch instructions +-- target a particular label. We have to insert fixup code to make +-- the register assignments from the different sources match up. -- type BlockAssignment - = BlockMap (FreeRegs, RegMap Loc) + = BlockMap (FreeRegs, RegMap Loc) -- | Where a vreg is currently stored --- A temporary can be marked as living in both a register and memory --- (InBoth), for example if it was recently loaded from a spill location. --- This makes it cheap to spill (no save instruction required), but we --- have to be careful to turn this into InReg if the value in the --- register is changed. - --- This is also useful when a temporary is about to be clobbered. We --- save it in a spill location, but mark it as InBoth because the current --- instruction might still want to read it. +-- A temporary can be marked as living in both a register and memory +-- (InBoth), for example if it was recently loaded from a spill location. +-- This makes it cheap to spill (no save instruction required), but we +-- have to be careful to turn this into InReg if the value in the +-- register is changed. + +-- This is also useful when a temporary is about to be clobbered. We +-- save it in a spill location, but mark it as InBoth because the current +-- instruction might still want to read it. -- data Loc - -- | vreg is in a register - = InReg !RealReg + -- | vreg is in a register + = InReg !RealReg - -- | vreg is held in a stack slot - | InMem {-# UNPACK #-} !StackSlot + -- | vreg is held in a stack slot + | InMem {-# UNPACK #-} !StackSlot - -- | vreg is held in both a register and a stack slot - | InBoth !RealReg - {-# UNPACK #-} !StackSlot - deriving (Eq, Show, Ord) + -- | vreg is held in both a register and a stack slot + | InBoth !RealReg + {-# UNPACK #-} !StackSlot + deriving (Eq, Show, Ord) instance Outputable Loc where - ppr l = text (show l) + ppr l = text (show l) -- | Get the reg numbers stored in this Loc. @@ -74,64 +74,64 @@ regsOfLoc (InMem _) = [] -- | Reasons why instructions might be inserted by the spiller. --- Used when generating stats for -ddrop-asm-stats. +-- Used when generating stats for -ddrop-asm-stats. -- data SpillReason - -- | vreg was spilled to a slot so we could use its - -- current hreg for another vreg - = SpillAlloc !Unique + -- | vreg was spilled to a slot so we could use its + -- current hreg for another vreg + = SpillAlloc !Unique - -- | vreg was moved because its hreg was clobbered - | SpillClobber !Unique + -- | vreg was moved because its hreg was clobbered + | SpillClobber !Unique - -- | vreg was loaded from a spill slot - | SpillLoad !Unique + -- | vreg was loaded from a spill slot + | SpillLoad !Unique - -- | reg-reg move inserted during join to targets - | SpillJoinRR !Unique + -- | reg-reg move inserted during join to targets + | SpillJoinRR !Unique - -- | reg-mem move inserted during join to targets - | SpillJoinRM !Unique + -- | reg-mem move inserted during join to targets + | SpillJoinRM !Unique -- | Used to carry interesting stats out of the register allocator. data RegAllocStats - = RegAllocStats - { ra_spillInstrs :: UniqFM [Int] } + = RegAllocStats + { ra_spillInstrs :: UniqFM [Int] } -- | The register alloctor state data RA_State - = RA_State + = RA_State - { - -- | the current mapping from basic blocks to - -- the register assignments at the beginning of that block. - ra_blockassig :: BlockAssignment + { + -- | the current mapping from basic blocks to + -- the register assignments at the beginning of that block. + ra_blockassig :: BlockAssignment - -- | free machine registers - , ra_freeregs :: {-#UNPACK#-}!FreeRegs + -- | free machine registers + , ra_freeregs :: {-#UNPACK#-}!FreeRegs - -- | assignment of temps to locations - , ra_assig :: RegMap Loc + -- | assignment of temps to locations + , ra_assig :: RegMap Loc - -- | current stack delta - , ra_delta :: Int + -- | current stack delta + , ra_delta :: Int - -- | free stack slots for spilling - , ra_stack :: StackMap + -- | free stack slots for spilling + , ra_stack :: StackMap - -- | unique supply for generating names for join point fixup blocks. - , ra_us :: UniqSupply + -- | unique supply for generating names for join point fixup blocks. + , ra_us :: UniqSupply - -- | Record why things were spilled, for -ddrop-asm-stats. - -- Just keep a list here instead of a map of regs -> reasons. - -- We don't want to slow down the allocator if we're not going to emit the stats. - , ra_spills :: [SpillReason] } + -- | Record why things were spilled, for -ddrop-asm-stats. + -- Just keep a list here instead of a map of regs -> reasons. + -- We don't want to slow down the allocator if we're not going to emit the stats. + , ra_spills :: [SpillReason] } -- | The register allocator monad type. newtype RegM a - = RegM { unReg :: RA_State -> (# RA_State, a #) } + = RegM { unReg :: RA_State -> (# RA_State, a #) } _______________________________________________ Cvs-ghc mailing list [email protected] http://www.haskell.org/mailman/listinfo/cvs-ghc
