Repository : ssh://darcs.haskell.org//srv/darcs/ghc On branch :
http://hackage.haskell.org/trac/ghc/changeset/a9b455c4b6960d47d31e769052104a4a4fc26cf0 >--------------------------------------------------------------- commit a9b455c4b6960d47d31e769052104a4a4fc26cf0 Author: Karel Gardas <[email protected]> Date: Sat Jul 9 17:54:30 2011 +0200 RTS: fix xchg/cas fcns to invoke memory barrier on ARMv7 platform This patch fixes RTS' xchg and cas functions. On ARMv7 it is recommended to add memory barrier after using ldrex/strex for implementing atomic lock or operation. >--------------------------------------------------------------- includes/stg/SMP.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h index df62e56..4162058 100644 --- a/includes/stg/SMP.h +++ b/includes/stg/SMP.h @@ -156,6 +156,9 @@ xchg(StgPtr p, StgWord w) " strex %1, %2, [%3]\n" " teq %1, #1\n" " beq 1b\n" +#if !defined(PRE_ARMv7) + " dmb\n" +#endif : "=&r" (result), "=&r" (tmp) : "r" (w), "r" (p) : "memory" @@ -225,6 +228,9 @@ cas(StgVolatilePtr p, StgWord o, StgWord n) " teq %0, #1\n" " it eq\n" " beq 1b\n" +#if !defined(PRE_ARMv7) + " dmb\n" +#endif : "=&r"(tmp), "=&r"(result) : "r"(p), "r"(o), "r"(n) : "cc","memory"); _______________________________________________ Cvs-ghc mailing list [email protected] http://www.haskell.org/mailman/listinfo/cvs-ghc
