Repository : ssh://darcs.haskell.org//srv/darcs/ghc On branch :
http://hackage.haskell.org/trac/ghc/changeset/330dff34ddc45eb0adc8d098a55f491cce0ea108 >--------------------------------------------------------------- commit 330dff34ddc45eb0adc8d098a55f491cce0ea108 Author: Karel Gardas <[email protected]> Date: Tue Jul 5 20:10:18 2011 +0200 implement ARMv6/7 specific xchg function >--------------------------------------------------------------- includes/stg/SMP.h | 20 ++++++++++++++++++-- 1 files changed, 18 insertions(+), 2 deletions(-) diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h index d093439..0b7592d 100644 --- a/includes/stg/SMP.h +++ b/includes/stg/SMP.h @@ -1,6 +1,6 @@ /* ---------------------------------------------------------------------------- * - * (c) The GHC Team, 2005-2009 + * (c) The GHC Team, 2005-2011 * * Macros for multi-CPU support * @@ -136,10 +136,26 @@ xchg(StgPtr p, StgWord w) : "+r" (result), "+m" (*p) : /* no input-only operands */ ); -#elif arm_HOST_ARCH +#elif arm_HOST_ARCH && defined(PRE_ARMv6) __asm__ __volatile__ ("swp %0, %1, [%2]" : "=&r" (result) : "r" (w), "r" (p) : "memory"); +#elif arm_HOST_ARCH && !defined(PRE_ARMv6) + // swp instruction which is used in PRE_ARMv6 code above + // is deprecated in AMRv6 and later. ARM, Ltd. *highly* recommends + // to use ldrex/strex instruction pair for the same purpose + // see chapter: Synchronization and semaphores in ARM Architecture + // Reference manual + StgWord tmp; + __asm__ __volatile__ ( + "1: ldrex %0, [%3]\n" + " strex %1, %2, [%3]\n" + " teq %1, #1\n" + " beq 1b\n" + : "=&r" (result), "=&r" (tmp) + : "r" (w), "r" (p) + : "memory" + ); #elif !defined(WITHSMP) #error xchg() unimplemented on this architecture result = *p; _______________________________________________ Cvs-ghc mailing list [email protected] http://www.haskell.org/mailman/listinfo/cvs-ghc
