Repository : ssh://darcs.haskell.org//srv/darcs/ghc On branch : ghc-7.4
http://hackage.haskell.org/trac/ghc/changeset/83c23b58941cd857343bab4c34e8209f2b9d4bee >--------------------------------------------------------------- commit 83c23b58941cd857343bab4c34e8209f2b9d4bee Author: Karel Gardas <[email protected]> Date: Tue Feb 14 08:01:47 2012 +0100 fix ARM's StgCRun clobbered register list for both ARM and Thumb modes MERGED from commit f3f8c90638e38088c3c8ea251f5c8e54e4047fe7 >--------------------------------------------------------------- rts/StgCRun.c | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletions(-) diff --git a/rts/StgCRun.c b/rts/StgCRun.c index ade1537..3654b33 100644 --- a/rts/StgCRun.c +++ b/rts/StgCRun.c @@ -672,7 +672,21 @@ StgRun(StgFunPtr f, StgRegTable *basereg) { "ldmfd sp!, {r4-r10, fp, ip, lr}\n\t" : "=r" (r) : "r" (f), "r" (basereg), "i" (RESERVED_C_STACK_BYTES) - : "%r4", "%r5", "%r6", "%r8", "%r9", "%r10", "%r11", "%fp", "%ip", "%lr" +#if !defined(__thumb__) + /* In ARM mode, r11/fp is frame-pointer and so we cannot mark + it as clobbered. If we do so, GCC complains with error. */ + : "%r4", "%r5", "%r6", "%r7", "%r8", "%r9", "%r10", "%ip", "%lr" +#else + /* In Thumb mode r7 is frame-pointer and so we cannot mark it + as clobbered. On the other hand we mark as clobbered also + those regs not used in Thumb mode. Hard to judge if this is + needed, but certainly Haskell code is using them for + placing GHC's virtual registers there. See + includes/stg/MachRegs.h Please note that Haskell code is + compiled by GHC/LLVM into ARM code (not Thumb!), at least + as of February 2012 */ + : "%r4", "%r5", "%r6", "%r8", "%r9", "%r10", "%fp", "%ip", "%lr" +#endif ); return r; } _______________________________________________ Cvs-ghc mailing list [email protected] http://www.haskell.org/mailman/listinfo/cvs-ghc
