Displays detailed information about the CPU(s) gathered from the
CPUID instruction, and also determines the exact model of CPU(s).
Where /proc/cpuinfo shows features important to a system,
cpuid shows what every feature in each CPU's architecture does.
It is updated and released frequently to stay current with
Intel and AMD information and supports other vendors' chips.
See the project home page for more information:
https://etallen.com/cpuid.html
The following package has been upgraded in the Cygwin distribution:
- cpuid 20260220
For changes since the previous Cygwin release, see below or
/usr/share/doc/cpuid/ChangeLog after installation.
cpuid.protospec 2026-02-20
- Renamed cpuid.proto.spec to be more friendly to rpmbuild.
cpuid.man
- Added Intel doc 714069.
- Added Intel docs 869992 & 872188.
cpuid.c
- Added (0,6),(10,14),1 B0/B1 steppings, from ILPMDF*.
- Added 0x23/0/ebx: RDPMC_USR_DISABLE supported.
- Added 0x29/0/ebx NCI, NDD, NF support.
- Added 0x8000000a/ecx x2AVIC_EXT field.
Eliminated duplicate headers for each 0x8000000a register.
- Added 0x8000001f/ebx not vulnerable to SNP cache coherency flag, from LX*.
- Added 0x80000021/eax PerfEvtSel2 MSR PreciseRetire support.
- Added 0x80000025/ebx number of RMP segments reduced.
- Added 0x80860001/ecx Transmeta nominal core clock frequency.
- Added 0xa/edx TMA slots/cycle.
- Added 7/1/ebx SEC-TEE-ATTESTATION (which is not described).
- Added 7/1/edx SLSM: IA32_INTEGRITY_STATUS MSR.
- Added AMD TSA mitigation bits from LX* (not yet documented):
0x80000021/eax bit 5: VERW memory form mitigates TSA;
0x80000021/ecx bit 1: not vulnerable to TSA-SQ,
0x80000021/ecx bit 2: not vulnerable to TSA-L1
- Added d/0/eax APX EGPR description.
The bit isn't documented, but I infer its existence from the presence
of sub-leaf 19 with "APX EGPR" state.
- Added hypervisor+6/eax (Microsoft) use VMFUNC for alias map switch.
- Added preliminary synth & uarch decodings for (3,15),(0,1) Nova Lake
& (3,15),(0,3) Nova Lake-L.
- Added support for walking sub-leaves of 0x29, in case any additional
sub-leafs are defined.
- Added synth decoding for (0,6),(12,12) Intel Core Ultra 3xx.
- Added synth decoding for AMD EPYC 7A53 (Trento), based on info via
instlatx64 from geekbench.
- Added uarch decoding for (11,15),({9,10,12},*) to Zen 6 (TSMC N2).
No synth decoding for these yet.
- Added uarch synth for (0,6),(12,12) (Panther Lake): Cougar Cove+Darkmont.
- Added uarch synth for (0,6),(13,5) (Wildcat Lake): Cougar Cove+Darkmont.
- Change uarch decoding for (11,15),(8,*) to Zen 6, from LX* patch.
- Changed synth stepping for (0,6),(12,6,2) Arrow Lake-S/HX to just B0,
based on 834774-011 spec update typo correction.
- Changed uarch decoding for (0,6),(11,5) Atom from Skymont to Crestmont,
per SSG*. Evidently, Arrow Lake-U (mobile) uses the older cores.
- Changed uarch decoding for (11,15),(5,*) to Zen 6 (TSMC N2).
- Changed uarch synth for (0,6),(11,12) process to TSMC N3B, like other
Lion Cove/Skymont CPUs.
- Correct fallback for (0,6),(3,7),9 for when the brand wasn't
understood, to mention stepping D1 as well as D0.
- Corrected synth decoding for (0,6),(11,5): Core Ultra 2xxU.
- Corrected synth decoding for (0,6),(12,5): Core Ultra 2xxH.
- Expanded synth decoding for (0,6),(6,12) to include D-1800.
- For 0x23/4/ebx, corrected bit offsets for XER support to match updated
Intel docs, added XER R16-R31 support, and renamed existing fields to
be more descriptive.
- Generalized (0,6),(12,6) synth decoding to include Arrow Lake-HX.
- In decode_mp_synth & print_apic_synth, for AMD/HYGON CPU's, use the
0x80000026 topology information, if present.
It mirrors the logic for Intel's 0x1f leaf, but with a different set
of topological layers.
Also, v2TopoToCotopo is split into intel vs. amd variants.
- In do_real, moved loop intended to iterate over 0x80000026 sub-leaves
out of the block iterating over 0x0+ leaves, and into the block
iterating over 0x80000000+ leaves (bugfix).
- In synth decoding for (10,15),(6,0), differentiate EPYC 4000 from
Ryzen 7000 (both Raphael).
- In synth decoding for (11,15),(4,0-7), differentiate EPYC 4005 (Grado)
from Ryzen 9000 (Granite Ridge).
- Narrowed 0x28/1/eax length of capacity bit mask field.
- print_80000001_eax_transmeta: Added type field.
- print_80860001_eax: Added type field.
- print_80860001_ebx_ecx: Fixed leaf name typo.
- print_c0000001_edx: Added bit fields for PARALLAX, TM3, RNG2, PHE2,
and RSA hardware support, although many evidently are present in VIA
Isaiah, too.
- Renamed 0x80000021/eax FP512 is downgraded to FP256.
- Renamed 0x80000021/eax WRMSR to FS/GS base is not serializing.
- Renamed 7/0/edx field "fast short REP MOVSB" to match updated Intel docs.
- Renamed synth decoding for Zen5c Sorano (which came entirely from
early "leaks") to Turin-Dense.
- Update synth decoding for (11,15),(6,*) and (11,15),(7,*) with Ryzen AI 300.
- Updated (0,6),(10,13),1 stepping to include L0, from ILPMDF*.
- Updated synth decoding for (11,15),(5,0) Venice to report EPYC (6th Gen).
- Widened 0x80000021/ebx microcode patch size field to 16 bits.
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