https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;h=52f5af5c2f9cbeffb54c1ea3865703d986ecf29d
commit 52f5af5c2f9cbeffb54c1ea3865703d986ecf29d Author: Yaakov Selkowitz <[email protected]> Date: Thu Oct 22 12:33:37 2015 -0500 winsup/utils: add CPU cache variables to getconf(1) * getconf.c (conf_table): Add LEVEL*_CACHE_* variables. Signed-off-by: Yaakov Selkowitz <[email protected]> Diff: --- winsup/utils/ChangeLog | 4 ++++ winsup/utils/getconf.c | 15 +++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/winsup/utils/ChangeLog b/winsup/utils/ChangeLog index 66bfcb0..ac6eb98 100644 --- a/winsup/utils/ChangeLog +++ b/winsup/utils/ChangeLog @@ -1,3 +1,7 @@ +2015-10-22 Yaakov Selkowitz <[email protected]> + + * getconf.c (conf_table): Add LEVEL*_CACHE_* variables. + 2015-08-30 Corinna Vinschen <[email protected]> * cygcheck.cc (dump_sysinfo): Fix missing commas in products array. diff --git a/winsup/utils/getconf.c b/winsup/utils/getconf.c index 7e0b5f5..8732be1 100644 --- a/winsup/utils/getconf.c +++ b/winsup/utils/getconf.c @@ -357,6 +357,21 @@ static const struct conf_variable conf_table[] = { "POSIX2_UPE", SYSCONF, _SC_2_UPE }, { "POSIX2_VERSION", SYSCONF, _SC_2_VERSION }, /* implementation-specific values */ + { "LEVEL1_ICACHE_SIZE", SYSCONF, _SC_LEVEL1_ICACHE_SIZE }, + { "LEVEL1_ICACHE_ASSOC", SYSCONF, _SC_LEVEL1_ICACHE_ASSOC }, + { "LEVEL1_ICACHE_LINESIZE", SYSCONF, _SC_LEVEL1_ICACHE_LINESIZE }, + { "LEVEL1_DCACHE_SIZE", SYSCONF, _SC_LEVEL1_DCACHE_SIZE }, + { "LEVEL1_DCACHE_ASSOC", SYSCONF, _SC_LEVEL1_DCACHE_ASSOC }, + { "LEVEL1_DCACHE_LINESIZE", SYSCONF, _SC_LEVEL1_DCACHE_LINESIZE }, + { "LEVEL2_CACHE_SIZE", SYSCONF, _SC_LEVEL2_CACHE_SIZE }, + { "LEVEL2_CACHE_ASSOC", SYSCONF, _SC_LEVEL2_CACHE_ASSOC }, + { "LEVEL2_CACHE_LINESIZE", SYSCONF, _SC_LEVEL2_CACHE_LINESIZE }, + { "LEVEL3_CACHE_SIZE", SYSCONF, _SC_LEVEL3_CACHE_SIZE }, + { "LEVEL3_CACHE_ASSOC", SYSCONF, _SC_LEVEL3_CACHE_ASSOC }, + { "LEVEL3_CACHE_LINESIZE", SYSCONF, _SC_LEVEL3_CACHE_LINESIZE }, + { "LEVEL4_CACHE_SIZE", SYSCONF, _SC_LEVEL4_CACHE_SIZE }, + { "LEVEL4_CACHE_ASSOC", SYSCONF, _SC_LEVEL4_CACHE_ASSOC }, + { "LEVEL4_CACHE_LINESIZE", SYSCONF, _SC_LEVEL4_CACHE_LINESIZE }, { "_NPROCESSORS_CONF", SYSCONF, _SC_NPROCESSORS_CONF }, { "_NPROCESSORS_ONLN", SYSCONF, _SC_NPROCESSORS_ONLN }, { "_AVPHYS_PAGES", SYSCONF, _SC_AVPHYS_PAGES },
