On Aug 3 14:00, Houder wrote:
> On 2018-08-03 12:39, Corinna Vinschen wrote:
> > On Aug 3 11:27, Houder wrote:
> > > On 2018-08-03 09:36, Corinna Vinschen wrote:
> [snip]
>
> > > > In terms of x86_64, do we have to change the fenv stuff completely
> > > > to use only SSE opcodes? Does that make sense at all?
> > >
> > > Ho! I have to disappoint you here! I am not an expert at all.
> >
> > Thanks all the same for your detailed description. A quick search in
> > glibc shows that x86_64 FP exceptions in fact work somewhat different in
> > that it additionally reads and writes from the SSE control register,
> > e.g. sysdeps/x86_64/fpu/fesetenv.c:
> >
> > __asm__ ("fnstenv %0\n"
> > "stmxcsr %1" : "=m" (*&temp), "=m" (*&temp.__mxcsr));
> > [...]
> > __asm__ ("fldenv %0\n"
> > "ldmxcsr %1" : : "m" (temp), "m" (temp.__mxcsr));
>
> ? ... uhm, this also happens in Korn's implementation (Cygwin). Only
> Dave Korn verifies if SSE is present (does the machine have SSE?).Oops. Next time I check our code first. Promised :} Corinna -- Corinna Vinschen Please, send mails regarding Cygwin to Cygwin Maintainer cygwin AT cygwin DOT com Red Hat
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