On Sun, Aug 01, 2004 at 10:20:38AM -0500, J.A. Terranson wrote: > On Sat, 31 Jul 2004, Major Variola (ret) wrote: > > > Tyler D asked about how the NSA could be so far ahead. > > Besides their ability to make 2" sq. chips at 10% yield (not > > something a commercial entity could get away with) > > What, exactly, would be the point of doing this?
More gates == more processing. > > they can also *thin and glue* those chips into say stacks > > of 5 thinned die. > > As easily as you could do this to high efficiency chips. It's possible, using technologies like flip-chip. But its not as good as having everything on one die. The interconnects are limited in number and large in size, so they take up a lot of room. Stacked die are also more difficult to keep cool. > > 2" sq = 4 x performance > > How do you figure 4x performance on a 2" chip? Most of the chip > performance is tied to the total distance that signals must traverse > across the chip surface. 4x the gates (roughly) means 4x performance. Chip performance, especially for highly parellizable things like key cracking, is determined by the number of gates. Eric
