On Wednesday, December 25, 2019, 04:53:24 PM PST, Zenaan Harkness <[email protected]> wrote: On Wed, Dec 25, 2019 at 06:55:59PM +0000, jim bell wrote: > On Wednesday, December 25, 2019, 09:44:21 AM PST, jim bell ><[email protected]> wrote: > > >> >The New York Times: Chuck Peddle Dies at 82; His $25 Chip Helped Start the >>PC Age. > https://www.nytimes.com/2019/12/24/technology/chuck-peddle-dead.html >> >6502 microprocessor. >> I was a fan of the Z80 microprocessor, which I viewed as 'the 8080 done >> right'. https://en.wikipedia.org/wiki/Zilog_Z80 >> Single +5 supply, single-phase clock, TTL compatible I/O (except >> for the CLK, which was pulled to +5 with a resistor), and a decoded >> memory and I/O system.
>What does that mean (decoded memory, decoded IO)? The Z-80 has four signal lines to do memory and io: /MREQ, /IOREQ, /RD, and /WR/ https://en.wikipedia.org/wiki/Zilog_Z80 To do a memory read, the /MREQ line goes low, and then the /RD also goes low.To do a memory write, the /MREQ line goes low, and then the /WR also goes low.To do an I/O read, the /IORQ line goes low, and then the /RD also goes low.To do an I/O write, the /IORQ line goes low, and then the /WR also goes low. This is simple and straightforward. The 8080 had a much more complicated system, but it was solved by the use of an external control chip, the 8228/8238 "System controller and bus driver": https://www.datasheets360.com/pdf/-4828066515233335508This chip read the system state information from the 8080, and from it generated four signals: /MEM R , /MEM W ,/IO R, and /IO W .The 8228/8238 also buffered the eight data lines, D0-D7, because the 8080 wasn't really TTL compatible, nor was it capable of driving a large system bus. I considered the Z80 method superior: Because two clocks acted during a given memory cycle, they could control timing. The /MREQ clock could be used, almost directly and maybe directly, to generate the /RAS signal as an input to the DRAMs of the era. The /RD line could be used to turn on the data buffer from the memory chips back to the processor. And the /WR line could be applied, directly or with decoding, to the /WR of the DRAM chips of that era. Very little external circuitry was needed on a small system. There was also a small Intel chip, the 8224, which acted as a crystal clock oscillator, and generated the two non-overlapping clocks, phase 1 and phase 2, which were higher-than TTL clocks. (The Z80 had a single clock, which was almost TTL compatible, but it had to be pulled to +5 volts with a resistor. Of course, I couldn't really blame Intel for the weaknesses of the 8080: During that early 1970's period, Moore's law was working on a transistors-on-a-chip doubling time of somewhere between 12 and 18 months. Since the delay between the design of the 8080 and the Z80 was about 2 years, that means that the Z80 had about a 3x advantage in the number of transistors. Such an increase in the number of transistors solves a lot of problems. https://en.wikipedia.org/wiki/Transistor_count I think this graph sucks because it is difficult to read, even expanded. It also omits the 64180, and the various 68010, 68020, 68030, etc. Intel fixed most of the drawbacks of the 8080 in their 8085, but by then the Z80 had taken over. Jim Bell
