It seems CCDC can accept raw data and write it to DDR2 memory without modification. I think a device connected to video-in port (via DC4) either should generate VD (V sync), HD (H sync) and PCLK (pixel clock), or otherwise generate only PCLK and lets davinci source HD and VD, syncronizing data with these signals.
Are C_WEN and C_FIELD signals neccesary in this scheme? Regards, Carlos _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
