/* UBL Uart Boot code Mostly copied from u-boot */

.macro	ret	
	mov	pc,lr
.endm

.macro	reteq	
	moveq	pc,lr
.endm

.macro	retne	
	movne	pc,lr
.endm

.macro	enter
	str	lr,[sp,#-4]!
.endm

.macro	exit
	ldr	pc,[sp],#4
.endm

.globl _start
_start:

	nop		/*00*/
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop		/*20*/
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop		/*40*/
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop		/*60*/
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop		/*80*/
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop		/*A0*/
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop		/*C0*/
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop		/*E0*/
	nop
	nop
	nop
	nop
	nop
	nop
	nop


.text
.org	0x100

	/*** Setup SVC + Thumb modes ***/

	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0
	bl	Rinit

	/*** Critical Setup Disable TLB MMU Caches***/

	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
	mcr	p15, 0, r0, c1, c0, 0
	
	/*** Mask Interrupts ***/

	mov	r1, #0x00000000
	ldr	r0, EINT_ENABLE0
	str	r1, [r0]
	ldr	r0, EINT_ENABLE1
	str	r1, [r0]

	/*------------------------------------------------------*
	 * Put the GEM in reset		    		  *
 	 *------------------------------------------------------*/

      /* Put the GEM in reset */
  	LDR R8, PSC_GEM_FLAG_CLEAR
	LDR R6, MDCTL_GEM
	LDR R7, [R6]
	AND R7, R7, R8
	STR R7, [R6]

	/* Enable the Power Domain Transition Command */
	LDR R6, PTCMD_0
	LDR R7, [R6]
	ORR R7, R7, #0x2
	STR R7, [R6]

	/* Check for Transition Complete(PTSTAT) */
checkStatClkStopGem:
	LDR R6, PTSTAT_0
	LDR R7, [R6]
    	AND R7, R7, #0x2
    	CMP R7, #0x0
    	BNE checkStatClkStopGem

	/* Check for GEM Reset Completion */
checkGemStatClkStop:
	LDR R6, MDSTAT_GEM
	LDR R7, [R6]
    	AND R7, R7, #0x100
    	CMP R7, #0x0
    	BNE checkGemStatClkStop

	/* Do this for enabling a WDT initiated reset this is a workaround
	   for a chip bug.  Not required under normal situations */
	LDR R6, P1394
	MOV R10, #0x0	
	STR R10, [R6]

	/*------------------------------------------------------*
	 * Enable L1 & L2 Memories in Fast mode                 *
	 *------------------------------------------------------*/
	LDR R6, DFT_ENABLE
	MOV R10, #0x1
	STR R10, [R6]

	LDR R6, MMARG_BRF0
	LDR R10, MMARG_BRF0_VAL
	STR R10, [R6]

	LDR R6, DFT_ENABLE
	MOV R10, #0x0
	STR R10, [R6]
	/*------------------------------------------------------*
	 * DDR2 PLL Intialization			    	*
 	 *------------------------------------------------------*/
	
      /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
	MOV R10, #0x0
	LDR R6, PLL2_CTL   
	LDR R7, PLL_CLKSRC_MASK
	LDR R8, [R6]
	AND R8, R8, R7
	MOV R9, R10, LSL #0x8
	ORR R8, R8, R9
	STR R8, [R6]
	
	/* Select the PLLEN source */
	LDR R7, PLL_ENSRC_MASK
	AND R8, R8, R7
	STR R8, [R6]
	
	/* Bypass the PLL */
	LDR R7, PLL_BYPASS_MASK
	AND R8, R8, R7
	STR R8, [R6]
	
	/* Wait for few cycles to allow PLLEN Mux switches properly to bypass Clock */
	MOV R10, #0x20 
WaitPPL2Loop:
    	SUB R10, R10, #0x1
    	CMP R10, #0x0
    	BNE WaitPPL2Loop	

     /* Reset the PLL */
    	LDR R7, PLL_RESET_MASK	
	AND R8, R8, R7
	STR R8, [R6]

     /* Power up the PLL */
    	LDR R7, PLL_PWRUP_MASK	
	AND R8, R8, R7
	STR R8, [R6]

     /* Enable the PLL from Disable Mode */
    	LDR R7, PLL_DISABLE_ENABLE_MASK	
	AND R8, R8, R7
	STR R8, [R6]

	/* Program the PLL Multiplier */
	LDR R6, PLL2_PLLM
	/*MOV R2, #0x13 Orig value */
	/*MOV R2, #0xB 165MHz */
	MOV R2, #0xD /* 189 MHz */
	STR R2, [R6]   /* R2 */

	/* Program the PLL2 Divisior Value */
	LDR R6, PLL2_DIV1
	/*MOV R3, #0x1 Orig */
	MOV R3, #0x0
	STR R3, [R6]    /* R3 */

	/* Program the PLL2 Divisior Value */
	LDR R6, PLL2_DIV2
	/*MOV R4, #0x9 Orig */
	/*MOV R4, #0x5 165MHz */
	MOV R4, #0x6 /* 189 MHz */
	STR R4, [R6]    /* R4 */

      /* PLL2 DIV1 MMR */
	LDR R8, PLL2_DIV_MASK
	LDR R6, PLL2_DIV1	
	LDR R9, [R6]
	AND R8, R8, R9
	MOV R9, #0X1
	MOV R9, R9, LSL #15
	ORR R8, R8, R9
	STR R8, [R6]

	/* Program the GOSET bit to take new divier values */
	LDR R6, PLL2_PLLCMD
	LDR R7, [R6]
	ORR R7, R7, #0x1
	STR R7, [R6]

      /* Wait for Done */
    	LDR R6, PLL2_PLLSTAT
doneLoop_0:    
    	LDR R7, [R6]
    	AND R7, R7, #0x1
    	CMP R7, #0x0
    	BNE doneLoop_0

      /* PLL2 DIV2 MMR */
	LDR R8, PLL2_DIV_MASK
	LDR R6, PLL2_DIV2	
	LDR R9, [R6]
	AND R8, R8, R9
	MOV R9, #0X1
	MOV R9, R9, LSL #15
	ORR R8, R8, R9
	STR R8, [R6]

	/* Program the GOSET bit to take new divier values */
	LDR R6, PLL2_PLLCMD
	LDR R7, [R6]
	ORR R7, R7, #0x1
	STR R7, [R6]

     /* Wait for Done */
    	LDR R6, PLL2_PLLSTAT
doneLoop:    
    	LDR R7, [R6]
    	AND R7, R7, #0x1
    	CMP R7, #0x0
    	BNE doneLoop
    				
	/* Wait for PLL to Reset Properly */
	MOV R10, #0x218  
ResetPPL2Loop:
    	SUB R10, R10, #0x1
    	CMP R10, #0x0
    	BNE ResetPPL2Loop
    
    	/* Bring PLL out of Reset */
    	LDR R6, PLL2_CTL    	
    	LDR R8, [R6]
    	ORR R8, R8, #0x08
    	STR R8, [R6]
     	
     /* Wait for PLL to Lock */
	LDR R10, PLL_LOCK_COUNT    
PLL2Lock:
    	SUB R10, R10, #0x1
    	CMP R10, #0x0
    	BNE PLL2Lock
    
     /* Enable the PLL */
    	LDR R6, PLL2_CTL    	
    	LDR R8, [R6]
    	ORR R8, R8, #0x01
    	STR R8, [R6]

	/*------------------------------------------------------*
	 * Issue Soft Reset to DDR Module		    		  *
 	 *------------------------------------------------------*/

      /* Shut down the DDR2 LPSC Module */
  	LDR R8, PSC_FLAG_CLEAR
	LDR R6, MDCTL_DDR2_0
	LDR R7, [R6]
	AND R7, R7, R8
	ORR R7, R7, #0x3
	STR R7, [R6]  

	/* Enable the Power Domain Transition Command */
	LDR R6, PTCMD_0
	LDR R7, [R6]
	ORR R7, R7, #0x1
	STR R7, [R6]    
	
	/* Check for Transition Complete(PTSTAT) */
checkStatClkStop:	
	LDR R6, PTSTAT_0
	LDR R7, [R6]
    	AND R7, R7, #0x1	
    	CMP R7, #0x0
    	BNE checkStatClkStop  
    
	/* Check for DDR2 Controller Enable Completion */
checkDDRStatClkStop:	
	LDR R6, MDSTAT_DDR2_0
	LDR R7, [R6]
    	AND R7, R7, #0x1F	
    	CMP R7, #0x3
    	BNE checkDDRStatClkStop  

	/*------------------------------------------------------*
	 * Program DDR2 MMRs for 135MHz Setting	    		  *
 	 *------------------------------------------------------*/
	
	/* Program PHY Control Register */
	LDR R6, DDRCTL
	LDR R7, DDRCTL_VAL
	STR R7, [R6]

	/* Program SDRAM Bank Config Register */
	LDR R6, SDCFG
	LDR R7, SDCFG_VAL
	STR R7, [R6]

	/* Program SDRAM TIM-0 Config Register */
	LDR R6, SDTIM0
	LDR R7, SDTIM0_VAL_135MHz
	STR R7, [R6]		

	/* Program SDRAM TIM-1 Config Register */
	LDR R6, SDTIM1
	LDR R7, SDTIM1_VAL_135MHz
	STR R7, [R6]		

	/* Program the SDRAM Bang Config Control Register */
	LDR R10, MASK_VAL
	LDR R8, SDCFG
	LDR R9, SDCFG_VAL
	AND R9, R9, R10
	STR R9, [R8]

	/* Program SDRAM TIM-1 Config Register */
	LDR R6, SDREF
	LDR R7, SDREF_VAL
	STR R7, [R6]		

        /*------------------------------------------------------*
         * Issue Soft Reset to DDR Module                                 *
         *------------------------------------------------------*/
                                                                                
        /* Issue a Dummy DDR2 read/write */
        LDR R8, DDR2_VAL
        LDR R7, DUMMY_VAL
        STR R7, [R8]
        LDR R7, [R8]
                                                                                
      /* Shut down the DDR2 LPSC Module */
        LDR R8, PSC_FLAG_CLEAR
        LDR R6, MDCTL_DDR2_0
        LDR R7, [R6]
        AND R7, R7, R8
        ORR R7, R7, #0x1
        STR R7, [R6]
                                                                                
        /* Enable the Power Domain Transition Command */
        LDR R6, PTCMD_0
        LDR R7, [R6]
        ORR R7, R7, #0x1
        STR R7, [R6]
                                                                                
        /* Check for Transition Complete(PTSTAT) */
checkStatClkStop2:
        LDR R6, PTSTAT_0
        LDR R7, [R6]
        AND R7, R7, #0x1
        CMP R7, #0x0
        BNE checkStatClkStop2
                                                                                
        /* Check for DDR2 Controller Enable Completion */
checkDDRStatClkStop2:
        LDR R6, MDSTAT_DDR2_0
        LDR R7, [R6]
        AND R7, R7, #0x1F
        CMP R7, #0x1
        BNE checkDDRStatClkStop2

        /*------------------------------------------------------*
         * Turn DDR2 Controller Clocks On                                 *
         *------------------------------------------------------*/
                                                                                
     /* Enable the DDR2 LPSC Module */
        LDR R6, MDCTL_DDR2_0
        LDR R7, [R6]
        ORR R7, R7, #0x3
        STR R7, [R6]
                                                                                
        /* Enable the Power Domain Transition Command */
        LDR R6, PTCMD_0
        LDR R7, [R6]
        ORR R7, R7, #0x1
        STR R7, [R6]
                                                                                
        /* Check for Transition Complete(PTSTAT) */
checkStatClkEn2:
        LDR R6, PTSTAT_0
        LDR R7, [R6]
        AND R7, R7, #0x1
        CMP R7, #0x0
        BNE checkStatClkEn2
                                                                                
        /* Check for DDR2 Controller Enable Completion */
checkDDRStatClkEn2:
        LDR R6, MDSTAT_DDR2_0
        LDR R7, [R6]
        AND R7, R7, #0x1F
        CMP R7, #0x3
        BNE checkDDRStatClkEn2
                                                                                
        /*  DDR Writes and Reads */
        LDR R6, CFGTEST
        MOV R3, #0x1
        STR R3, [R6]    /* R3 */

	/*------------------------------------------------------*
	 * System PLL Intialization			    		  *
 	 *------------------------------------------------------*/

      /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
	MOV R2, #0x0
	LDR R6, PLL1_CTL   
	LDR R7, PLL_CLKSRC_MASK
	LDR R8, [R6]
	AND R8, R8, R7
	MOV R9, R2, LSL #0x8
	ORR R8, R8, R9
	STR R8, [R6]
	
	/* Select the PLLEN source */
	LDR R7, PLL_ENSRC_MASK
	AND R8, R8, R7
	STR R8, [R6]
	
	/* Bypass the PLL */
	LDR R7, PLL_BYPASS_MASK
	AND R8, R8, R7
	STR R8, [R6]
	
	/* Wait for few cycles to allow PLLEN Mux switches properly to bypass Clock */
	MOV R10, #0x20 

WaitLoop:
    	SUB R10, R10, #0x1
    	CMP R10, #0x0
    	BNE WaitLoop	

     /* Reset the PLL */
    	LDR R7, PLL_RESET_MASK	
	AND R8, R8, R7
	STR R8, [R6]

      /* Disable the PLL */
    	ORR R8, R8, #0x10    
    	STR R8, [R6]

      /* Power up the PLL */
    	LDR R7, PLL_PWRUP_MASK	
	AND R8, R8, R7
	STR R8, [R6]

      /* Enable the PLL from Disable Mode */
    	LDR R7, PLL_DISABLE_ENABLE_MASK	
	AND R8, R8, R7
	STR R8, [R6]

	/* Program the PLL Multiplier */
	LDR R6, PLL1_PLLM
	/*MOV R3, #0x10  As per Amit, PLL should be in normal mode i.e X by 16 */
	/*MOV R3, #0x11  As per Ebby 486 MHz */
	MOV R3, #0x14 /* For 567MHz */
	STR R3, [R6]      

	/* Wait for PLL to Reset Properly */
	MOV R10, #0xFF 

ResetLoop:
    	SUB R10, R10, #0x1
    	CMP R10, #0x0
    	BNE ResetLoop
    
      /* Bring PLL out of Reset */
    	LDR R6, PLL1_CTL    	
    	ORR R8, R8, #0x08
    	STR R8, [R6]
     	
      /* Wait for PLL to Lock */
	LDR R10, PLL_LOCK_COUNT    

PLL1Lock:
    	SUB R10, R10, #0x1
    	CMP R10, #0x0
    	BNE PLL1Lock
    
      /* Enable the PLL */
    	ORR R8, R8, #0x01
    	STR R8, [R6]

	nop
	nop	
	nop
	nop

	bl	Rinit

	/*------------------------------------------------------*
	 * AEMIF configuration for NOR Flash (double check)     *
	 *------------------------------------------------------*/

 	LDR R0, WAITCFG   
	LDR R1, WAITCFG_VAL 
	LDR R2, [R0]
	ORR R2, R2, R1
	STR R2, [R0]    

	LDR R0, ACFG3
	LDR R1, ACFG3_VAL
	LDR R2, [R0]
	AND R1, R2, R1
	STR R1, [R0]

	LDR R0, ACFG4
	LDR R1, ACFG4_VAL
	LDR R2, [R0]
	AND R1, R2, R1
	STR R1, [R0]

	LDR R0, ACFG5
	LDR R1, ACFG5_VAL
	LDR R2, [R0]
	AND R1, R2, R1
	STR R1, [R0]     

	/*--------------------------------------*
	 * VTP manual Calibration               *
	 *--------------------------------------*/
	LDR R0, VTPIOCR
	LDR R1, VTP_MMR0
	STR R1, [R0]

	LDR R0, VTPIOCR
	LDR R1, VTP_MMR1
	STR R1, [R0]
	
     /* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */

		MOV R10,#0x5B0   
VTPLock:	SUB R10,R10,#0x1
    		CMP R10,#0x0
    		BNE VTPLock

	LDR R6, DFT_ENABLE
	MOV R10, #0x1
	STR R10, [R6]

	LDR R6, DDRVTPR
	LDR R7, [R6]
	AND R7, R7, #0x1F
	AND R8, R7, #0x3E0
	ORR R8, R7, R8
	LDR R7, VTP_RECAL
	ORR R8, R7, R8
	LDR R7, VTP_EN
	ORR R8, R7, R8
	STR R8, [R0]


     /* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */

		LDR R10,=0x5B0   
VTP1Lock:	SUB R10,R10,#0x1
    		CMP R10,#0x0
    		BNE VTP1Lock

	LDR R1, [R0]
	BIC R2,R2,#0x00002000
	LDR R2, VTP_MASK
	AND R2, R1, R2
	STR R2, [R0]

	LDR R6, DFT_ENABLE
	MOV R10, #0x0
	STR R10, [R6]
	
	ldr	sp,STACK_TOP

Cloop:	ldr	r0,RDBmsg
	bl	Puts
	bl	Getc
	bl	Putc
	cmp	r0,#'?'
	beq	Help
	cmp	r0,#'d'
	beq	Mems 
	cmp	r0,#'z'
	beq	Reset 
	cmp	r0,#'u'
	beq	Uboot 
	cmp	r0,#'l'
	beq	Rload
	cmp	r0,#'n'
	beq	Rload
	cmp	r0,#'o'
	beq	Rload
	cmp	r0,#'r'
	beq	Rrom
	cmp	r0,#'g'
	beq	Rgo
	b	Cloop

Rinit:	ldr	r0,INITTAB
Rinit1:	ldr	r1,[r0],#4
	cmp	r1,#0
	reteq
	ldr	r2,[r0],#4
	str	r2,[r1]
	b	Rinit1
	
Help:	ldr	r0,HELPmsg
	bl	Puts
	b	Cloop

Mems:	bl	Pcrlf
	mov	r6,#8
Mems1:	ldr	r0,CURaddr
	bl	Pmem
	ldr	r0,CURaddr
	add	r0,r0,#16
	str	r0,CURaddr
	subs	r6,r6,#1
	bne	Mems1
	b	Cloop

Reset:	ldr	pc,TCROMstart
Uboot:	ldr	pc,ROMstart

/*** Some really nice subroutines ***/

Puth:	and	r0,r0,#0xF
	add	r0,r0,#'0'
	cmp	r0,#'9'
	addgt	r0,r0,#7
Putc:	ldr	r2,UART0_IOR
Putc1:	ldr	r1,[r2,#0x14]
	tst	r1,#0x20 
	beq	Putc1
	str	r0,[r2]
	ret
Puta:	and	r0,r0,#0xFF
	cmp	r0,#32
	movlt	r0,#'.'
	cmp	r0,#126
	movgt	r0,#'.'
	b	Putc

Getc:	ldr	r1,UART0_IOR
Getc1:	ldr	r0,[r1,#0x14]
	tst	r0,#0x01 
	beq	Getc1
	ldr	r0,[r1]
	ret

Puts:	ldr	r2,UART0_IOR
Puts1:	ldrb	r3,[r0],#1
	cmp	r3,#0
	reteq	
Puts2:	ldr	r1,[r2,#0x14]
	tst	r1,#0x20 
	beq	Puts2
	str	r3,[r2]
	b	Puts1

Geth:	enter
	bl	Getc
	mov	r2,r0
	bl	Getc
	orr	r2,r2,r0,lsl#8
	bl	Getc
	orr	r2,r2,r0,lsl#16
	bl	Getc
	orr	r0,r2,r0,lsl#24
	exit

Pspace:	enter
	mov	r0,#' '
	bl	Putc
	exit

Pcrlf:	enter
	mov	r0,#'\r'
	bl	Putc
	mov	r0,#'\n'
	bl	Putc
	exit

Pasc:	enter
	mov	r4,r0
	mov	r0,r4
	bl	Puta
	mov	r0,r4, lsr #8
	bl	Puta
	mov	r0,r4, lsr #16
	bl	Puta
	mov	r0,r4, lsr #24
	bl	Puta
	exit

Phex:	enter
	mov	r4,r0 
	mov	r0,r4, lsr #28
	bl	Puth
	mov	r0,r4, lsr #24
	bl	Puth
	mov	r0,r4, lsr #20
	bl	Puth
	mov	r0,r4, lsr #16
	bl	Puth
	mov	r0,r4, lsr #12
	bl	Puth
	mov	r0,r4, lsr #8
	bl	Puth
	mov	r0,r4, lsr #4
	bl	Puth
	mov	r0,r4
	bl	Puth
	exit

Pmem:	enter
	mov	r5,r0
	bl	Phex
	bl	Pspace	
	bl	Pspace
	ldr	r0,[r5]
	bl	Phex
	bl	Pspace	
	ldr	r0,[r5,#4]
	bl	Phex
	bl	Pspace	
	ldr	r0,[r5,#8]
	bl	Phex
	bl	Pspace	
	ldr	r0,[r5,#12]
	bl	Phex
	bl	Pspace
	bl	Pspace
	ldr	r0,[r5]
	bl	Pasc
	ldr	r0,[r5,#4]
	bl	Pasc
	ldr	r0,[r5,#8]
	bl	Pasc
	ldr	r0,[r5,#12]
	bl	Pasc
	bl	Pcrlf	
	exit
	
/* loader
/* Format: 
/* XXXX - Load address  (R3)
/* XXXX - Data length   (R4)
/* XXXX - Start address (R5)
/* XX.. - Data */	
	
Rload:	bl	Geth		/* Load Address */
	mov	r3,r0
	bl	Geth		/* Length (Bytes) */
	mov	r4,r0
Rload1:	bl	Getc		/* Load the Data */
	strb	r0,[r3],#1
	subs	r4,r4,#1
	bne	Rload1
	ldr	r0,RLmsg
	bl	Puts
	b	Cloop	
	
Rrom:	bl	Geth		/* Load Address */
	mov	r3,r0
	bl	Geth		/* Length (Bytes) */
	mov	r4,r0
Rrom1:	ldrb	r0,[r3],#1
	bl	Putc
	subs	r4,r4,#1
	bne	Rrom1
	ldr	r0,RLmsg
	bl	Puts
	b	Cloop	
	
Rgo:	bl	Geth		/* Load Address */
	mov	pc,r0
	
	/* the literal pools origin */

	ldr	r6,=0x6996 

ROMstart:	.word	0x02000000
RAMstart:	.word	0x80000000
TCROMstart:	.word	0x00004000
TCRAMstart:	.word	0x00000000
CURaddr:	.word	0x00000000


_PINMUX0:		.word 0x01C40000
_PINMUX1:		.word 0x01C40004
CHP_SHRTSW:		.word 0x01C40038
DFT_ENABLE:		.word 0x01C4004C
PLL1_CTL:		.word 0x01C40900 
PLL1_PLLM:		.word 0x01C40910
PLL2_CTL:		.word 0x01C40D00 
PLL2_PLLM:		.word 0x01C40D10
PLL2_DIV1:		.word 0x01C40D1C
PLL2_DIV2:		.word 0x01C40D18
PLL2_PLLCMD:		.word 0x01C40D38
PLL2_PLLSTAT:		.word 0x01C40D3C	
PLL2_BPDIV:		.word 0x01C40D2C

MDCTL_DDR2:		.word 0x01C41A34
PTCMD:			.word 0x01C41120
PTSTAT:			.word 0x01C41128
MDSTAT_DDR2:		.word 0x01C41834
MDCTL_TPCC:		.word 0x01C41A08
MDSTAT_TPCC:		.word 0x01C41808
MDCTL_TPTC0:		.word 0x01C41A0C
MDSTAT_TPTC0:		.word 0x01C4180C
MDCTL_TPTC1:		.word 0x01C41A10
MDSTAT_TPTC1:		.word 0x01C41810
MDCTL_TPCC_SYNC:	.word 0x01C41A08
MDSTAT_TPCC_SYNC:	.word 0x01C41808
MDCTL_TPTC0_SYNC:	.word 0x01C41A0C
MDSTAT_TPTC0_SYNC:	.word 0x01C4180C
MDCTL_TPTC1_SYNC:	.word 0x01C41A10
MDSTAT_TPTC1_SYNC:	.word 0x01C41810
PTCMD_SYNC:		.word 0x01C41120
PTSTAT_SYNC:		.word 0x01C41128
PD1_CTL:		.word 0x01C41304
EPCPR:			.word 0x01C41070
EPCCR:			.word 0x01C41078
MDCTL_GEM:		.word 0x01C41A9C
MDSTAT_GEM:		.word 0x01C4189C
MDCTL_IMCOP:		.word 0x01C41AA0
MDSTAT_IMCOP:		.word 0x01C418A0
PTCMD_0:		.word 0x01C41120
PTSTAT_0:		.word 0x01C41128
P1394:			.word 0x01C41a20
MDCTL_DDR2_0:		.word 0x01C41A34
MDSTAT_DDR2_0:		.word 0x01C41834


DDRVTPR:		.word 0x01C42030  /* DDR VPTR MMR */
DFT_BASEADDR:		.word 0x01C42000
MMARG_BRF0:		.word 0x01C42010     /* BRF margin mode 0     (Read / write)*/
MMARG_G10:		.word 0x01C42018     /*GL margin mode 0      (Read / write)*/


FIQ0_CLEAR:		.word 0x01C48000
FIQ1_CLEAR:		.word 0x01C48004
IRQ0_CLEAR:		.word 0x01C48008
IRQ1_CLEAR:		.word 0x01C4800C
EINT_ENABLE0:		.word 0x01C48018
EINT_ENABLE1:		.word 0x01C4801C


AEMIF_BASE_ADDR:	.word 0x01E00000
WAITCFG:         	.word 0x01E00004
ACFG2:           	.word 0x01E00010
ACFG3:           	.word 0x01E00014
ACFG4:           	.word 0x01E00018
ACFG5:           	.word 0x01E0001C

REG_TC_EMIFS_CONFIG:		.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG:	.word 0xfffecc10
REG_TC_EMIFS_CS1_CONFIG:	.word 0xfffecc14
REG_TC_EMIFS_CS2_CONFIG:	.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG:	.word 0xfffecc1c



_DEV_SETTING:			.word 0x00000C1F


WAITCFG_VAL:     	.word 0x0
ACFG2_VAL:       	.word 0x3FFFFFFD
ACFG3_VAL:       	.word 0x3FFFFFFD
ACFG4_VAL:       	.word 0x3FFFFFFD
ACFG5_VAL:       	.word 0x3FFFFFFD


DDR2DEBUG:		.word 0x8FFFF000


/* EINT0 register */

CLEAR_FLAG:				.word 0xFFFFFFFF
EDMA_PARAM0_D_S_BIDX_VAL: 	.word 0x00010001
PSC_FLAG_CLEAR:			.word 0xFFFFFFE0
PSC_GEM_FLAG_CLEAR:			.word 0xFFFFFEFF

DATA_MAX:				.word 0x0000FFFF
SPIN_ADDR:				.word 0x00003FFC   /* ARM PC value(B $) for the DSP Test cases */
SPIN_OPCODE:			.word 0xEAFFFFFE

/* Interrupt Clear Register */
/* DDR2 MMR & CONFIGURATION VALUES for 75 MHZ */
DDRCTL:				.word	0x200000E4
SDREF:				.word	0x2000000C
SDCFG:				.word	0x20000008
SDTIM0:				.word	0x20000010
SDTIM1:				.word	0x20000014
SDSTAT:				.word 0x20000004
VTPIOCR:				.word 0x200000F0  /* VTP IO Control register */
VTP_MMR0:				.word 0x201F
VTP_MMR1:				.word 0xA01F
PCH_MASK:				.word 0x3E0
VTP_MASK:				.word 0xFFFFDFFF
VTP_RECAL:				.word 0x40000
VTP_EN:					.word 0x02000


CFGTEST:				.word	0x80010000
					
DDRCTL_VAL:				.word	0x50006405
SDCFG_VAL:				.word	0x00008832
MASK_VAL:                    	.word 0x00000FFF
SDTIM0_VAL_135MHz:		.word	0x30923A91
SDTIM1_VAL_135MHz:		.word	0x0019c722
SDREF_VAL:				.word 0x000005c3

/* GEM Power Up & LPSC Control Register */

PLL_CLKSRC_MASK: 			.word 0xFFFFFEFF  /* Mask the Clock Mode bit and it is programmble through the run script */
PLL_ENSRC_MASK:  			.word 0xFFFFFFDF  /* Select the PLLEN source */
PLL_BYPASS_MASK: 			.word 0xFFFFFFFE  /* Put the PLL in BYPASS, eventhough the device */
PLL_RESET_MASK:  			.word 0xFFFFFFF7  /* Put the PLL in Reset Mode */
PLL_PWRUP_MASK:  			.word 0xFFFFFFFD  /* PLL Power up Mask Bit  */
PLL_DISABLE_ENABLE_MASK:	.word 0xFFFFFFEF  /* Enable the PLL from Disable */
PLL_LOCK_COUNT:          	.word 0x2000

/* PLL1-SYSTEM PLL MMRs */
PLL2_DIV_MASK:			.word 0xFFFF7FFF


DLLPWRUPMASK:			.word 0xFFFFFFEF
DDR2_ADDR:			.word 0x80000000

MMARG_BRF0_VAL:			.word 0x00444400
DDR2_VAL:			.word 0x80000000
DUMMY_VAL:			.word 0xA55AA55A
UART0_IOR:		.word 0x01C20000
UART0_LSR:		.word 0x01C20014
STACK_TOP:		.word 0x00004000

			
INITTAB:		.word	.-0xFC
			.word 	0x01C40000,0x00000C1F	/* PINMUX0 */
			.word 	0x01C40004,0x00000001	/* PINMUX1 */

			.word	0x01C20030,0x0000E003	/* UART0 POW */
			.word	0x01C20008,0x00000000	/* UART0 FCR */
			.word	0x01C2000C,0x00000003	/* UART0 LCR */
			.word	0x01C20010,0x00000000	/* UART0 MCR */
			.word	0x01C20020,0x0000000E	/* UART0 DL0 */
			.word	0x01C20024,0x00000000	/* UART0 DL1 */
			.word	0x01C20000,0x00000065	/* UART0 THR */

			
			.word	0			/* That's all */

	.align	2
RDBmsg:	.word	.-0xFC	
	.ascii	"\r\nRboot->\0"


			.align  2
HELPmsg:		.word	.-0xFC
			.ascii	"\r\nRudy's Wonderful UBL.\n\r"
			.ascii	"d  - Display Memory\r\n"
			.ascii	"l  - Load Program/Data\r\n"
			.ascii	"g  - Goto Address\r\n"
			.ascii	"z  - Reset\r\n"
			.ascii	"u  - Start U-Boot\r\n\0"
			.align 2
RLmsg:			.word	.-0xFC
			.ascii	"Done.\r\n#\0"

.ltorg

Literals: