As you can select only 27MHz, PLL2(378MHz)/N, VPBECLK and PCLK as CLK_VENC, you can't get exact 65MHz from current PLL2 setting. (ref. sprue37 3.1.1.3)
The following setting generates 63MHz as DCLK. # DCLK <- CLK_VENC/1 DCLKCTL(0x01c72464) <- 0x0800 DCLKPTN0(0x01c72468) <- 0x0001 # select CLK_VENC source VPSS_CLKCTL(0x01c40044) <- 0x0009 # set PLL2 DIV1 to generate 63MHz PLLDIV1(0x01c40d18) <- 0x0005 PLLDIV1(0x01c40d18) <- 0x8005 If you need exact 65MHz, solder R268, input 65MHz clock to VPBECLK(DC5-19) and select VPBECLK as CLK_VENC. Regards, Hiroshi _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
