I am using EVM6446 platform and DVSDK enviroment to develop an ARM
client + DSP video codec application.
As you know, for multi-processor co-operation, the cache coherency is a
very important issue.
e.g., For a ARM client + dsp algo application, some important rules
about cache coherency should be performed:
for ARM side:
(1) each time before ARM client invoke an algo's processing interface,
ARM client should flush the relevant cache about input buffers
(2) each time after ARM client has invoked an algo's processing
interface, ARM client should invalidate the relevant cache about output
buffers
for DSP side:
(3) at the entry point of an algo's processing interface, the algo
should invalidate the relevant cache about input buffers
(4) at the exit point of an algo's processing interface, the algo
should flush the relevant cache about the output buffers,
Isn't it right?
while, during my experiments, i found that in the DSP trace file
generated by my dsp codec, it indicates that each time before algo
processing interface is invoked, XDAIS framework will do the cache
invalidating operation automatically, and after invoking the processing
interface, XDAIS framework will do the cache flushing operation
automatically...
e.g.:
@0x009d3001:[T:0x8f062fd4] OM - Memory_cacheInv> Enter(addr=0x8a66a000,
sizeInBytes=13) //invalidate cache for inbuf
@0x009d3031:[T:0x8f062fd4] OM - Memory_cacheInv> return
@0x009d304e:[T:0x8f062fd4] OM - Memory_cacheInv> Enter(addr=0x86c00000,
sizeInBytes=691200) //invalidate cache for outbuf
@0x009d336a:[T:0x8f062fd4] OM - Memory_cacheInv> return
@0x009d3388:[T:0x8f062fd4] ti.sdo.ce.video.VIDDEC - VIDDEC_process>
Enter (handle=0x8f062a58, inBufs=0x11f0f594, outBufs=0x11f0f5a0,
inArgs=0x8fe05a38, outArgs=0x8fe05a4c)
@0x009d35f8:[T:0x8f062fd4] ti.sdo.ce.video.VIDDEC - VIDDEC_process> Exit
(handle=0x8f062a58, retVal=0xffffffff)
@0x009d3632:[T:0x8f062fd4] OM - Memory_cacheWbInv>
Enter(addr=0x86c00000, sizeInBytes=691200) //flush cache
for outbuf
@0x009d3950:[T:0x8f062fd4] OM - Memory_cacheWbInv> return
Based on these oberservation, i suppose that DSP XDAIS framework will
automatically do the cache coherency operations for algo, so algo need
not do these operations any more.
Isn't it right?
But in these two days, i encounted a problem about dirty data. i.e.,
the data readen by dsp sometimes are not consistent with the data
written by arm. and after i add cache invalidating operation for the
input bitstream at the entry point of dsp algo processing interface, it
seems ok.
now, i feel very wield.
anyway, whether should the algo creator do the cache coherency
operations manually at the dsp side?
BR,
Zhou
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