Hi
I am planning to put some documentation at www.fl-eng.com for the davinci,
but here is a snap shot
The following function was used to drive a 1024x768 DVI flat panel display.
The DVI was implemented using the TFP410 and we produced an RGB888 output
from the Davinci. You need to make sure the PINMUX0 register is configured
for LCD888 mode to enable the lower bits of the RGB output bus from the
davinci. Also we needed make sure that the LCD_OE signal was enabled because
this is used to qualify when the RGB data is being transmitted from the
6446M. The TFP410 DVI encoder needs the LCD_OE signal to know when to encode
RGB or HSYNC/VSYNC onto the DVI interface.
If you aren't using the DVI via a TFP410 type device, the same info should
still apply to a standard LCD device.
static void davincifb_rgb_config(int on)
{
DBGENTER;
char data[10];
char temp[20];
unsigned int hsync,hactive,hfront,hback;
unsigned int vsync,vactive,vfront,vback;
unsigned int hint,vint;
int notfound=1;
memset(temp,0,sizeof(temp));
memset(data,0,sizeof(data));
printk("** Configuring for RGB Video Mode\r\n");
if (on) {
/* Reset video encoder module */
dispc_reg_out(VENC_VMOD, 0);
dispc_reg_out(VENC_VMOD,0x2013); // start video encoder in
RGB mode
dispc_reg_out(VENC_VIDCTL,0x2000); // enable video clock
output
dispc_reg_out(VENC_SYNCCTL,0x000F); // hsync + vsync are on
active low polarity
dispc_reg_out(VENC_DCLKCTL,0x0800);
dispc_reg_out(VENC_DCLKPTN0,0x0001);
dispc_reg_out(VPSS_CLKCTL,0x0009);
// generate 63MHz DCLK
dispc_reg_out(VPSS_PLLDIV1,0x0009);
dispc_reg_out(VPSS_PLLDIV1,0x8009);
/*
// standard video modes
CLK
640x480, 60Hz 25.175 640 16 96 48 480 11 2
31
640x480, 72Hz 31.500 640 24 40 128 480 9 3
28
640x480, 75Hz 31.500 640 16 96 48 480 11 2
32
640x480, 85Hz 36.000 640 32 48 112 480 1 3
25
800x600, 56Hz 38.100 800 32 128 128 600 1 4
14
800x600, 60Hz 40.000 800 40 128 88 600 1 4
23
800x600, 72Hz 50.000 800 56 120 64 600 37 6
23
800x600, 75Hz 49.500 800 16 80 160 600 1 2
21
800x600, 85Hz 56.250 800 32 64 152 600 1 3
27
1024x768, 60Hz 65.000 1024 24 136 160 768 3 6
29
1024x768, 70Hz 75.000 1024 24 136 144 768 3 6
29
*/
// horizontal sync pulse width
hsync=135;
hactive=1024;
hfront=24;
hback=160;
vactive=768;
vsync=20;
vfront=3;
vback=10;
hint=hsync+hactive+100; // pad so we can slide the LCD_OE so we can make
sure we catch all the CTL signals
vint=vsync+vactive;
hfront=hfront+hsync;
dispc_reg_out(VENC_HSPLS,hsync);
dispc_reg_out(VENC_HINT,hint);
dispc_reg_out(VENC_HSTART,hfront);
dispc_reg_out(VENC_HVALID,hactive);
dispc_reg_out(VENC_VSPLS,vsync);
dispc_reg_out(VENC_VINT,vint);
dispc_reg_out(VENC_VSTART,vfront);
dispc_reg_out(VENC_VVALID,vactive);
dispc_reg_out(VENC_HSDLY,0);
dispc_reg_out(VENC_VSDLY,0);
// crazy part#1000
// these registers are barely documented but they are
// key to keeping the OSD module and the VENC module synced
// set these bits to basically NOT-GATE the OSD clock
dispc_reg_out(VENC_OSDCLK0,0xffff);
dispc_reg_out(VENC_OSDCLK1,0xffff);
dispc_reg_out(VENC_OSDHAD,50); // advance the timing? why
not
// dont cull anything!
dispc_reg_out(VENC_HVLDCL0,0xffffffff);
dispc_reg_out(VENC_HVLDCL1,0xffffffff);
dispc_reg_out(VENC_LCDOUT,0x0001); // enable LCD_OE to
active high
dispc_reg_out(VENC_RGBCTL,0); // stadnard RGB output
printk ("Seeking TFP410 DVI Encoder....\r\n");
// get device ID register
data[0]=0x00;
davinci_i2c_write (1, data, TFP410);
davinci_i2c_read (2, temp, TFP410);
printk("*** Device ID = 0x%02x%02x\r\n",temp[0],temp[1]);
if (temp[0]==0x10 && temp[1]==0x04)
{
printk("Located TFP410....\r\n");
notfound=0;
}
else
{
printk("TFP410 not found...critical fault....\r\n");
// while(1)
// {
// }
}
printk("Configuring TFP410 Interface device\r\n");
data[0]=0x08; // select CTL_1
data[1]=0x07;
davinci_i2c_write (2, data, TFP410);
// generate color bars
// dispc_reg_out(VENC_VDPRO,0x0100);
/* Enable Composite output and start video encoder */
// dispc_reg_out(VENC_VMOD, (VENC_VMOD_VIE | VENC_VMOD_VENC));
/* Set REC656 Mode */
// dispc_reg_out(VENC_YCCCTL, 0x1);
/* Enable output mode and NTSC */
// dispc_reg_out(VENC_VMOD, 0x1003);
/* Enable Component output; DAC A: Y, DAC B: Pb, DAC C: Pr
*/
// dispc_reg_out(VENC_DACSEL, 0x543);
/* Enable all DACs */
// dispc_reg_out(VENC_DACTST, 0);
} else {
/* Reset video encoder module */
dispc_reg_out(VENC_VMOD, 0);
}
DBGEXIT;
}
-----Original Message-----
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of
Anthony P. Lannutti
Sent: Tuesday, November 28, 2006 11:41 AM
To: [email protected]
Subject: RE: Davinci-linux-open-source Digest, Vol 11, Issue 77
When I was working on attaching an LCD to the DVEVM I had the same
questions. Attached are 2 PDF files with as much explanation as I was able
to get. I believe the DCLKCTL.pdf is an excerpt from a new version of the
Video Processing Back End (VPBE) User's Guide (sprue37.pdf) and the other is
pages 57-61 of the TMS320DM6446 datasheet (sprs283c.pdf) showing the
VPSS_CLK_CTRL register description. Be aware, it seems that in different
documents this register is called VPSS_CLK, VPSS_CLKCTL or VPSS_CLK_CTRL,
all referring to the same register.
Regards,
Tony
-----Original Message-----
Message: 3
Date: Tue, 28 Nov 2006 17:11:17 +0100
From: Lorenzo Lutti <[EMAIL PROTECTED]>
Subject: Re: Undocummented registers
To: davinci-linux-open-source
<[email protected]>
Message-ID: <[EMAIL PROTECTED]>
Content-Type: text/plain; charset=ISO-8859-15; format=flowed
Hiroshi Uchino ha scritto:
>> 0x01C4 0044 VPSS_CLKCTL (VPSS clock control)
> tms320dm6446.pdf 3.3.2.2
There is no such paragraph in the 6446 datasheet, and VPSS_CLKCTL isn't
described in any datasheet. This is becoming very frustrating... :(
Cheers, Lorenzo
------------------------------
Message: 4
Date: Tue, 28 Nov 2006 17:11:09 +0100
From: Lorenzo Lutti <[EMAIL PROTECTED]>
Subject: VPBE undocumented registers
To: davinci-linux-open-source
<[email protected]>
Message-ID: <[EMAIL PROTECTED]>
Content-Type: text/plain; charset=ISO-8859-15; format=flowed
I'm trying to connect a little RGB display to the EVM; I need to change
basically all the default parameters (pixel frequency, behaviour of LCD_OE,
etc...), and therefore I've entered the wonderful world of the undocumented
registers such as DCLKCTL, VPSS_CLK, VPSS_CLKCTL and a truckload of others
referenced everywhere but never described.
Where can I find the documentation of these arcane registers?
Cheers, Lorenzo
*********************
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