Hi Emanualle,
The support for 525p is planned to be included in the
latest release of the drivers.
The approx code for it looks something like this:
vpbe_set_display_default();
/* Reset video encoder module */
dispc_reg_out(VENC_VMOD, 0);
dispc_reg_out(OSD_BASEPX, dm->videomode.basepx);
dispc_reg_out(OSD_BASEPY, dm->videomode.basepy);
dispc_reg_out(VPSS_CLKCTL, 0x19);
dispc_reg_merge(VPBE_PCR, VPBE_PCR_VENC_DIV,
VPBE_PCR_VENC_DIV);
dispc_reg_out(VENC_OSDCLK0, 0);
dispc_reg_out(VENC_OSDCLK1, 1);
dispc_reg_merge(VENC_VDPRO, VENC_VDPRO_DAFRQ,
VENC_VDPRO_DAFRQ);
dispc_reg_merge(VENC_VDPRO, VENC_VDPRO_DAUPS,
VENC_VDPRO_DAUPS);
/* Enable Composite output and start video encoder */
/* Set VMOD to select VENC =ENABLE,
TVTYP = HDTV 525, HDMD = HDTV, ITLC = Non_interlace */
dispc_reg_out(VENC_VMOD, (VENC_VMOD_VIE | VENC_VMOD_VENC));
dispc_reg_merge(VENC_VMOD,
VENC_VMOD_VDMD_YCBCR8 <<
VENC_VMOD_VDMD_SHIFT, VENC_VMOD_VDMD);
dispc_reg_merge(VENC_VMOD, VENC_VMOD_HDMD, VENC_VMOD_HDMD);
dispc_reg_merge(VENC_VMOD,
HDTV_525P << VENC_VMOD_TVTYP_SHIFT,
VENC_VMOD_TVTYP);
/* Enable Component output; DAC A: Y, DAC B: Pb, DAC C: Pr */
dispc_reg_out(VENC_DACSEL, 0x543);
/* Set REC656 Mode */
dispc_reg_out(VENC_YCCCTL, 0x1);
/* Enable all DACs */
dispc_reg_out(VENC_DACTST, 0);
Please see if this can help you. Please get back if you need any
clarifications.
Thanks and Regards,
-Manju
------------------------------------------------------------------------
*From:* [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] *On
Behalf Of *Emanuele Ghidoli
*Sent:* Monday, January 29, 2007 10:58 PM
*To:* [email protected]
*Subject:* VPFE - 525p settings
Hello,
I want to run DVEMV to EDTV timings (525p).
I modify the linux driver in this way:
In the static int davincifb_probe(*struct* device *dev)
{
printk("Setting Up Clocks for DM420 OSD\n"); //* Initialize the
VPSS Clock Control register *//
dispc_reg_out(VPSS_CLKCTL, 0x19); /// 0x19 old value 0x18 (27MHz
clock)/
printk(KERN_INFO "Enabling vsync and hsync output\n"); //* Ghido -
Enable VYSNC and HSYNC output *//
dispc_reg_merge( VENC_VIDCTL, 0, VENC_VIDCTL_SYDIR); //* Ghido -
Enable VSYNC and HSYNC signals *//
dispc_reg_out( VENC_SYNCCTL, 0xF);
etc...
and create this function:
static void davincifb_vga_rgb_config(int on)
{
DBGENTER;
*if* (on) {
//* Reset video encoder module *//
dispc_reg_out(VENC_VMOD, 0);
//* Enable Composite output and start video encoder *//
dispc_reg_out(VENC_VMOD, ( VENC_VMOD_VENC));
//* Video encoder clock divisor set to 1 (for progressive) *//
dispc_reg_out(VPBE_PCR, VPBE_PCR_VENC_DIV);
//* Set REC656 Mode *//
dispc_reg_out(VENC_YCCCTL, 0x1);
//* set RGB LPF sampling frequency to ENC clock / 2 *//
dispc_reg_merge(VENC_RGBCTL, 0x0200, 0x0200);
//* Ghido - Enable output mode and NTSC progressive *//
dispc_reg_out(VENC_VMOD, 0x1103);///0x0103);/
//* Ghido - Say to DAC that it is running to 54 MHz *//
dispc_reg_merge(VENC_VDPRO, VENC_VDPRO_DAFRQ|0x7, VENC_VDPRO_DAFRQ|0x7);
///|0x300 for test/
//* Ghido - Say to DAC to go in RGB mode and remove sync on green*//
dispc_reg_merge(VENC_CMPNT, VENC_CMPNT_MRGB,
VENC_CMPNT_MRGB|VENC_CMPNT_MSYG);
//* Enable Component output; DAC A: Y, DAC B: Pb, DAC C: Pr *//
dispc_reg_out(VENC_DACSEL, 0x543);
//* Enable all DACs *//
dispc_reg_out(VENC_DACTST, 0);
} *else* {
//* Reset video encoder module *//
dispc_reg_out(VENC_VMOD, 0);
}
DBGEXIT;
}
I add this function in the correct position. I add some defines to manage this
but...
When I enable colorbar I see the colorbar in the correct way but when I try to
use the framebuffer the image is completely scrambled.
Anyone tried to do this or have some idea?
Thank you.
Emanuele Ghidoli
