Roberto Waltman wrote:
R. Simning wrote:
> I am using mmap(..) to allow user space to view physical addresses.
> This has worked well when I am using it to view registers within the
> Davinci. My problems occur when I try to use mmap(..) to view a FPGA
> connected to CE3. I cannot read the contents from Linux application.
>>
> if ((imc->sLinux.uiDevMemFd=open("/dev/mem",O_RDWR|O_SYNC))==-1)
> return (FALSE);
> imc->sLinux.vpCE3base=( U8 *) mmap((void*) 0x04000000, 4096,
> PROT_READ|PROT_WRITE|PROT_EXEC,
> MAP_SHARED,imc->sLinux.uiDevMemFd, 0x04000000);
> if (imc->sLinux.vpCE3base !=(U8 *)0x04000000)
> return FALSE;
This is not necessarily an error, the first
parameter to mmap()is only a hint.
The OS may map the EMIF at 0x04000000 correctly,
but return a pointer with a value other than
0x04000000.
Try:
U32 map_offset;
...
imc->sLinux.vpCE3base=
(U8*) mmap((void*) 0x04000000,
4096,
PROT_READ|PROT_WRITE|PROT_EXEC,
MAP_SHARED,
imc->sLinux.uiDevMemFd,
0x04000000);
if (imc->sLinux.vpCE3base == MAP_FAILED)
return FALSE;
map_offset = imc->sLinux.vpCE3base - (U8*) 0x04000000;
U8 read_u8(U8 *addr)
{
return *(addr + map_offset)
}
void write_u8(U8 *addr, U8 data)
{
*(addr + map_offset) = data
}
>
> if ((imc->uiRegFd=open("/dev/mem",O_RDWR|O_SYNC))==-1)
> return (FALSE);
> imc->puiRegs=( U32 *) mmap((void *) 0x01e00000, 4096,
> PROT_READ|PROT_WRITE|PROT_EXEC, MAP_SHARED,imc->uiRegFd,
> 0x01e00000);
>
> imc->puiRegs[5]=0x8f2479c;
>
> Any ideas what I am doing wrong?
I am doing almost exactly the same with no problems.
Differences
(a) I supply 0 as the first parameter to mmap() and
handle the offset as shown above
(b) I do not use PROT_EXEC (do you really need it?).
There could also be a data size mismatch. Make sure that any pointer
used has or is casted to the correct type.
You may also need to call msync() to flush changes.
Roberto Waltman
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Thanks for the help.
Unfortunately the suggested changes had no effect.
I modified my code to continually loop on a read of the first location
within CE3 space with a 1/2 second loop delay and looked at the signals
with a scope. What I found was not one access, but bursts of 278
accesses at a period of 1/2 second. It appears when I attempt to read a
single byte from CE3, the hardware actually attempts to read a burst
consecutive accesses. The period between bursts is approximately 1/2
second and the period between individual accesses within the burst is
approximately 37.3 usec.
Bob
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