Hi,all There is anyone to do some work with vpbe user's guide about digital display interface?
I see digital display interface and do some hardware to it. I use "2.2.2.1 YCC8 Signal Interface Description" and bt.656 mode. And I patch the newly kernel about digital lcd, but I can't see this lcd mode. As this doc: *ITU-R BT.656 format output is optionally available in YCC8 mode and is enabled via YCCCTL.R656. In this mode, the YCbCr output timing and output order is fixed by hardware in order to conform to the standard and they cannot be altered by user. To use BT656 mode, the VENC must operate in the standard mode (VIDCTL.VDMD = 0). Note that this mode operates correctly only when the pixel clock frequency is half of the VENC clock. In this mode, the sync signals are embedded within the data stream and HSYNC/VSYNC are inactive.* ** I can't know this word : "*Note that this mode operates correctly only when the pixel clock frequency is half of the VENC clock."* ** Maybe my VENC's clk is setting 54M from ddr2 ??? Now I setting it 27M and vclk is out 27M too. ** Kernel setting: /* Configure VMOD. No change in VENC bit */ dispc_reg_out(VENC_VMOD, 0x1010 | venc); /* Set REC656 Mode */ dispc_reg_out(VENC_YCCCTL, 0x1); There is any other setting ? Can we chat about davinci ? My msn is: [EMAIL PROTECTED] -- Communication is not a problem, but a chance! MAIl to: [EMAIL PROTECTED]
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