Hi,
I am running my CE algo and client app all on the DSP side. I am having a problem with cache coherency. In the DSP client side I am populating a buffer in DDR2 with some test data. In the DSP algo side, I am using EDMA to transfer this data from DDR2 to L1DSRAM. The problem is that the first 64 bytes of the transferred buffer are garbled. Looking at the memory viewer, the first 64 bytes of my DDR2 buffer are in L1D Cache. So my question is whether the CE runtime will flush the cache in all cases, or only when managing client/algo scenarios across ARM & DSP boundaries? Thanks! Ben
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