/* * regdump - tool to display a given group of DaVinci processor registers * * (c) Copyright 2007 by Optelecom-NKF BV * set under the GPLv2 * * 2007-08-28 amuijnck initial version, main OK but dumpers not yet complete */ #include #include #include #include #include #include #include #include #include typedef unsigned int u32; //----------------------------------------------------------------------- // read a 32-bit word from a physical address //----------------------------------------------------------------------- static u32 getu32(u32 addr) { void *map, *regaddr; u32 val; static int fd = -1; // fd for /dev/mem static u32 pagesize; // corresponding page size if (fd == -1) // open map file only once { fd = open("/dev/mem", O_RDWR | O_SYNC); if (fd < 0) { perror("open(\"/dev/mem\")"); exit(1); } pagesize = getpagesize(); // we can map only complete pages } map = mmap(0, // map a page to given physical location pagesize, PROT_READ | PROT_WRITE, MAP_SHARED, fd, addr & ~(pagesize - 1)); // truncate physical to pagesize if (map == (void *) -1) { perror("mmap()"); exit(1); } regaddr = map + (addr & (pagesize - 1)); // virtual page + physical offset in page val = *(u32 *) regaddr; // get the physical value munmap(0, pagesize); // release page again return val; } //----------------------------------------------------------------------- // dump a single register + description //----------------------------------------------------------------------- void dumpreg(u32 addr, char* description) { // addr value desc printf("%08X: %08X %s\n", addr, getu32(addr), description); } //----------------------------------------------------------------------- // dump DDR2 controller //----------------------------------------------------------------------- void dump_ddr(void) { printf("--- DDR2 ------------------------------\n"); dumpreg( 0x20000004, "SDRSTAT status " ); dumpreg( 0x20000008, "SDBCR bank config" ); dumpreg( 0x2000000c, "SDRCR refresh ctrl" ); dumpreg( 0x20000010, "SDTIMR timing" ); dumpreg( 0x20000014, "SDTIMR2 ,," ); dumpreg( 0x20000020, "PBBPR ddr2 pri inversion max bursts" ); dumpreg( 0x200000c0, "IRR interrupt raw" ); dumpreg( 0x200000c4, "IMR interrupt mask" ); dumpreg( 0x200000c8, "IMSR interrupt mask set" ); dumpreg( 0x200000cc, "IMCR interrupt mask clear" ); dumpreg( 0x200000e4, "DDRPHYCR PHY ctrl" ); dumpreg( 0x200000f0, "VTPIOCR VTP IO ctrl" ); dumpreg( 0x01c42030, "DDR2VTP termination control" ); } //----------------------------------------------------------------------- // dump DMA controller //----------------------------------------------------------------------- // support: print the global + 4 shadow regions of an EDMA register set static void dumpdma4(u32 addr, char* description) { // addr glob sh0 sh1 sh2 sh3 desc printf("%08X: %08X %08X %08X %08X %08X %s\n", addr, getu32(addr), getu32(addr+0x1000), getu32(addr+0x1200), getu32(addr+0x1400), getu32(addr+0x1600), description); } // support: print the TC0 and TC1 columns of an EDMA TC register set static void dumpdmat(u32 addr, char* description) { // addr TC0 TC1 desc printf("%08X: %08X %08X %s\n", addr, getu32(addr), getu32(addr+0x400), description); } void dump_dma(void) { printf("--- EDMA ------------------------------\n"); dumpreg( 0x01c00004, "CCCFG config" ); dumpreg( 0x01c00200, "QCHMAP0 qdma chan map" ); dumpreg( 0x01c00204, "QCHMAP1 ,," ); dumpreg( 0x01c00208, "QCHMAP2 ,," ); dumpreg( 0x01c0020c, "QCHMAP3 ,," ); dumpreg( 0x01c00210, "QCHMAP4 ,," ); dumpreg( 0x01c00214, "QCHMAP5 ,," ); dumpreg( 0x01c00218, "QCHMAP6 ,," ); dumpreg( 0x01c0021c, "QCHMAP7 ,," ); dumpreg( 0x01c00240, "DMAQNUM0 dma queue nr" ); dumpreg( 0x01c00244, "DMAQNUM1 ,," ); dumpreg( 0x01c00248, "DMAQNUM2 ,," ); dumpreg( 0x01c0024c, "DMAQNUM3 ,," ); dumpreg( 0x01c00250, "DMAQNUM4 ,," ); dumpreg( 0x01c00254, "DMAQNUM5 ,," ); dumpreg( 0x01c00258, "DMAQNUM6 ,," ); dumpreg( 0x01c0025c, "DMAQNUM7 ,," ); dumpreg( 0x01c00260, "DMAQNUM cc qdma queue nr"); dumpreg( 0x01c00284, "QUEPRI queue pri" ); dumpreg( 0x01c00300, "EMR event mis" ); dumpreg( 0x01c00304, "EMRH ,, hi" ); dumpreg( 0x01c00308, "EMCR event mis clr" ); dumpreg( 0x01c0030c, "EMCRH ,, hi" ); dumpreg( 0x01c00310, "QEMR qdma event mis" ); dumpreg( 0x01c00314, "QEMCR qdmq event mis clr" ); dumpreg( 0x01c00318, "CCERR edma3cc err" ); dumpreg( 0x01c0031c, "CCERRCLR edma3cc err clr" ); dumpreg( 0x01c00320, "EEVAL error evaluate" ); dumpreg( 0x01c00340, "DRAE0 dma region access ena"); dumpreg( 0x01c00344, "DRAEH0 ,, hi" ); dumpreg( 0x01c00348, "DRAE1 ,," ); dumpreg( 0x01c0034c, "DRAEH1 ,, hi" ); dumpreg( 0x01c00350, "DRAE2 ,," ); dumpreg( 0x01c00354, "DRAEH2 ,, hi" ); dumpreg( 0x01c00358, "DRAE3 ,," ); dumpreg( 0x01c0035c, "DRAEH3 ,, hi" ); dumpreg( 0x01c00380, "QRAE0 qdma region access ena" ); dumpreg( 0x01c00384, "QRAE1 ,," ); dumpreg( 0x01c00388, "QRAE2 ,," ); dumpreg( 0x01c0038c, "QRAE3 ,," ); dumpreg( 0x01c00400, "Q0E0 event Q0 entry" ); dumpreg( 0x01c00404, "Q0E1 ,," ); dumpreg( 0x01c00408, "Q0E2 ,," ); dumpreg( 0x01c0040c, "Q0E3 ,," ); dumpreg( 0x01c00410, "Q0E4 ,," ); dumpreg( 0x01c00414, "Q0E5 ,," ); dumpreg( 0x01c00418, "Q0E6 ,," ); dumpreg( 0x01c0041c, "Q0E7 ,," ); dumpreg( 0x01c00420, "Q0E8 ,," ); dumpreg( 0x01c00424, "Q0E9 ,," ); dumpreg( 0x01c00428, "Q0E10 ,," ); dumpreg( 0x01c0042c, "Q0E11 ,," ); dumpreg( 0x01c00430, "Q0E12 ,," ); dumpreg( 0x01c00434, "Q0E13 ,," ); dumpreg( 0x01c00438, "Q0E14 ,," ); dumpreg( 0x01c0043c, "Q0E15 ,," ); dumpreg( 0x01c00440, "Q1E0 event Q1 entry" ); dumpreg( 0x01c00444, "Q1E1 ,," ); dumpreg( 0x01c00448, "Q1E2 ,," ); dumpreg( 0x01c0044c, "Q1E3 ,," ); dumpreg( 0x01c00450, "Q1E4 ,," ); dumpreg( 0x01c00454, "Q1E5 ,," ); dumpreg( 0x01c00458, "Q1E6 ,," ); dumpreg( 0x01c0045c, "Q1E7 ,," ); dumpreg( 0x01c00460, "Q1E8 ,," ); dumpreg( 0x01c00464, "Q1E9 ,," ); dumpreg( 0x01c00468, "Q1E10 ,," ); dumpreg( 0x01c0046c, "Q1E11 ,," ); dumpreg( 0x01c00470, "Q1E12 ,," ); dumpreg( 0x01c00474, "Q1E13 ,," ); dumpreg( 0x01c00478, "Q1E14 ,," ); dumpreg( 0x01c0047c, "Q1E15 ,," ); dumpreg( 0x01c00600, "QSTAT0 queue 0 status" ); dumpreg( 0x01c00604, "QSTAT1 queue 1 status" ); dumpreg( 0x01c00620, "QWMTHRA queue watermark thresh A" ); dumpreg( 0x01c00640, "CCSTAT EDMA3CC status" ); // these register sets are printed in columns GLOBAL SHADOW0 SHADOW1 SHADOW2 SHADOW3 // 12345678: 12345678 12345678 12345678 12345678 12345678 printf(" global shadow0 shadow1 shadow2 shadow3\n"); dumpdma4( 0x01c01000, "ER event" ); dumpdma4( 0x01c01004, "ERH ,, hi" ); dumpdma4( 0x01c01008, "ECR event clr" ); dumpdma4( 0x01c0100c, "ECRH ,, hi" ); dumpdma4( 0x01c01010, "ESR event set" ); dumpdma4( 0x01c01014, "ESRH ,, hi" ); dumpdma4( 0x01c01018, "CER chain event" ); dumpdma4( 0x01c0101c, "CERH ,, hi" ); dumpdma4( 0x01c01020, "EER event ena" ); dumpdma4( 0x01c01024, "EERH ,, hi" ); dumpdma4( 0x01c01028, "EECR event ena clr" ); dumpdma4( 0x01c0102c, "EECRH ,, hi" ); dumpdma4( 0x01c01030, "EESR event ena set" ); dumpdma4( 0x01c01034, "EESRH ,, hi" ); dumpdma4( 0x01c01038, "SER sec. event" ); dumpdma4( 0x01c0103c, "SERH ,, hi" ); dumpdma4( 0x01c01040, "SECR sec. event clr" ); dumpdma4( 0x01c01044, "SECRH ,, hi" ); dumpdma4( 0x01c01050, "IER int ena" ); dumpdma4( 0x01c01054, "IERH ,, hi" ); dumpdma4( 0x01c01058, "IECR int ena clr" ); dumpdma4( 0x01c0105c, "IECRH ,, hi" ); dumpdma4( 0x01c01060, "IESR int ena set" ); dumpdma4( 0x01c01064, "IESRH ,, hi" ); dumpdma4( 0x01c01068, "IPR int pend" ); dumpdma4( 0x01c0106c, "IPRH ,, hi" ); dumpdma4( 0x01c01070, "ICR int clr" ); dumpdma4( 0x01c01074, "ICRH ,, hi" ); dumpdma4( 0x01c01078, "IEVAL int evaluate" ); dumpdma4( 0x01c01080, "QER qdma event" ); dumpdma4( 0x01c01084, "QEER qdma event ena" ); dumpdma4( 0x01c01088, "QEECR qdma event ena clr" ); dumpdma4( 0x01c0108c, "QEESR qdma event ena set" ); dumpdma4( 0x01c01080, "QSER qdma sec. event" ); dumpdma4( 0x01c01080, "QSECR qdma sec. event clr"); // these register sets are printed in columns TC0 TC1 // 12345678: 12345678 12345678 printf(" TC0 TC1\n"); dumpdmat( 0x01c10004, "TCCFG config" ); dumpdmat( 0x01c10100, "TCSTAT status" ); dumpdmat( 0x01c10120, "ERRSTAT error status" ); dumpdmat( 0x01c10124, "ERREN error enable" ); dumpdmat( 0x01c10128, "ERRCLR error clr" ); dumpdmat( 0x01c1012c, "ERRDET error details" ); dumpdmat( 0x01c10130, "ERRCMD error int cmd" ); dumpdmat( 0x01c10140, "RDRATE read rate" ); dumpdmat( 0x01c10240, "SAOPT src act options" ); dumpdmat( 0x01c10244, "SASRC src act addr" ); dumpdmat( 0x01c10248, "SACNT src act count" ); dumpdmat( 0x01c1024c, "SADST src act dest" ); dumpdmat( 0x01c10250, "SABIDB src act B-idx" ); dumpdmat( 0x01c10254, "SAMPPRXY src act mem prot" ); dumpdmat( 0x01c10258, "SACNTRLD src act count reload" ); dumpdmat( 0x01c1025c, "SASRCBREF src act src B-ref" ); dumpdmat( 0x01c10260, "SADSTBREF src act dst B-ref" ); dumpdmat( 0x01c10280, "DFCNTRLD dest fifo count reload" ); dumpdmat( 0x01c10284, "DFSRCBREF dest fifo src B-ref" ); dumpdmat( 0x01c10288, "DFDSTBREF dest fifo dst B-ref" ); dumpdmat( 0x01c10300, "DFOPT0 dest fifo options" ); dumpdmat( 0x01c10304, "DFSRC0 dest fifo src addr" ); dumpdmat( 0x01c10308, "DFCNT0 dest fifo count" ); dumpdmat( 0x01c1030c, "DFDST0 dest fifo dest addr" ); dumpdmat( 0x01c10310, "DFBIDX0 dest fifo B-idx" ); dumpdmat( 0x01c10314, "DFMPPRXY0 dest fifo mem prot proxy" ); dumpdmat( 0x01c10340, "DFOPT1 dest fifo options" ); dumpdmat( 0x01c10344, "DFSRC1 dest fifo src addr" ); dumpdmat( 0x01c10348, "DFCNT1 dest fifo count" ); dumpdmat( 0x01c1034c, "DFDST1 dest fifo dest addr" ); dumpdmat( 0x01c10350, "DFBIDX1 dest fifo B-idx" ); dumpdmat( 0x01c10354, "DFMPPRXY1 dest fifo mem prot proxy" ); dumpdmat( 0x01c10380, "DFOPT2 dest fifo options" ); dumpdmat( 0x01c10384, "DFSRC2 dest fifo src addr" ); dumpdmat( 0x01c10388, "DFCNT2 dest fifo count" ); dumpdmat( 0x01c1038c, "DFDST2 dest fifo dest addr" ); dumpdmat( 0x01c10390, "DFBIDX2 dest fifo B-idx" ); dumpdmat( 0x01c10394, "DFMPPRXY2 dest fifo mem prot proxy" ); dumpdmat( 0x01c103c0, "DFOPT3 dest fifo options" ); dumpdmat( 0x01c103c4, "DFSRC3 dest fifo src addr" ); dumpdmat( 0x01c103c8, "DFCNT3 dest fifo count" ); dumpdmat( 0x01c103cc, "DFDST3 dest fifo dest addr" ); dumpdmat( 0x01c103d0, "DFBIDX3 dest fifo B-idx" ); dumpdmat( 0x01c103d4, "DFMPPRXY3 dest fifo mem prot proxy" ); } //----------------------------------------------------------------------- // dump DMA parameter RAM (128 sets of 8 words) //----------------------------------------------------------------------- void dump_dmaparm(void) { int set, parm; // set 12345678 12345678 12345678 12345678 12345678 12345678 12345678 12345678 printf("set OPT SRC A_B_CNT DST S_D_BIDX LNK_BLD S_D_CIDX CCNT\n"); for (set=0; set < 128; set++) { printf("%3d", set); for (parm=0; parm < 8; parm++) { printf(" %08X", getu32(0x01c04000 + set * 32 + parm * 4)); } printf("\n"); } } //----------------------------------------------------------------------- // dump PLLs //----------------------------------------------------------------------- void dump_pll(void) { printf("--- PLL 1 -----------------------------\n"); dumpreg( 0x01c40800, "PID" ); dumpreg( 0x01c408E4, "RSTYPE" ); dumpreg( 0x01c40900, "PLLC" ); dumpreg( 0x01c40910, "PLLM" ); dumpreg( 0x01c40918, "PLLDIV1" ); dumpreg( 0x01c4091c, "PLLDIV2" ); dumpreg( 0x01c4091c, "PLLDIV2" ); dumpreg( 0x01c40920, "PLLDIV3" ); dumpreg( 0x01c40928, "POSTDIV" ); dumpreg( 0x01c4092c, "BPDIV" ); dumpreg( 0x01c40938, "PLLCMD" ); dumpreg( 0x01c4093c, "PLLSTAT" ); dumpreg( 0x01c40940, "ALNCTL" ); dumpreg( 0x01c40944, "DCHANGE" ); dumpreg( 0x01c40948, "CKEN" ); dumpreg( 0x01c4094c, "CKSTAT" ); dumpreg( 0x01c40950, "SYSTAT" ); dumpreg( 0x01c40960, "PLLDIV4" ); dumpreg( 0x01c40964, "PLLDIV5" ); dumpreg( 0x01c40C00, "PID" ); printf("--- PLL 2 -----------------------------\n"); dumpreg( 0x01c40D00, "PLLC" ); dumpreg( 0x01c40D10, "PLLM" ); dumpreg( 0x01c40D18, "PLLDIV1" ); dumpreg( 0x01c40D1c, "PLLDIV2" ); dumpreg( 0x01c40D20, "POSTDIV" ); dumpreg( 0x01c40D2c, "BPDIV" ); dumpreg( 0x01c40D38, "PLLCMD" ); dumpreg( 0x01c40D40, "ALNCTL" ); dumpreg( 0x01c40D44, "DCHANGE" ); dumpreg( 0x01c40D48, "CKEN" ); dumpreg( 0x01c40D4c, "CKSTAT" ); dumpreg( 0x01c40D50, "SYSTAT" ); } //----------------------------------------------------------------------- // dump all registers with priority info in them //----------------------------------------------------------------------- void dump_pri(void) { printf("--- Priorities ------------------------\n"); dumpreg( 0x01c4003C, "MSTPRI0 master pri (does nothing)" ); dumpreg( 0x01c40040, "MSTPRI1 master pri (does it all)" ); dumpreg( 0x01c73404, "VPSSPCR vpss pri" ); // dumpreg( 0x0182020c, "MDMAARBE c64+ dma pri (no ARM access!)" ); dumpreg( 0x01c00284, "EDMACCQUEPRI dma queue pri" ); dumpreg( 0x20000020, "PBBPR ddr2 pri inversion max bursts" ); dumpreg( 0x01c8016c, "TXFIFOCTRL emac fifo theshold" ); } //----------------------------------------------------------------------- // dump power supply and clock control //----------------------------------------------------------------------- void dump_psc(void) { printf("--- Power Supply and Clock Control ----\n"); dumpreg( 0x01c41000, "PID" ); dumpreg( 0x01c41010, "GBLCTL" ); dumpreg( 0x01c41018, "INTEVAL" ); dumpreg( 0x01c41040, "MERRPR0" ); dumpreg( 0x01c41044, "MERRPR1" ); dumpreg( 0x01c41050, "MERRCR0" ); dumpreg( 0x01c41054, "MERRCR1" ); dumpreg( 0x01c41060, "PERRPR" ); dumpreg( 0x01c41068, "PERRCR" ); dumpreg( 0x01c41070, "EPCPR" ); dumpreg( 0x01c41078, "EPCCR" ); dumpreg( 0x01c41100, "RAILSTAT" ); dumpreg( 0x01c41104, "RAILCTL" ); dumpreg( 0x01c41108, "RAILSEL" ); dumpreg( 0x01c41120, "PTCMD" ); dumpreg( 0x01c41128, "PTSTAT" ); dumpreg( 0x01c41200, "PDSTAT0" ); dumpreg( 0x01c41204, "PDSTAT1" ); dumpreg( 0x01c41300, "PDCTL0" ); dumpreg( 0x01c41304, "PDCTL1" ); dumpreg( 0x01c41510, "MCKOUT0" ); dumpreg( 0x01c41514, "MCKOUT1" ); dumpreg( 0x01c41600, "MDCFG0 vpss dma" ); dumpreg( 0x01c41604, "MDCFG1 vpss mmr" ); dumpreg( 0x01c41608, "MDCFG2 edmacc" ); dumpreg( 0x01c4160c, "MDCFG3 edmatc0" ); dumpreg( 0x01c41610, "MDCFG4 edmatc1" ); dumpreg( 0x01c41614, "MDCFG5 emac" ); dumpreg( 0x01c41618, "MDCFG6 emac mem ctl"); dumpreg( 0x01c4161c, "MDCFG7 mdio" ); dumpreg( 0x01c41620, "MDCFG8 --" ); dumpreg( 0x01c41624, "MDCFG9 usb" ); dumpreg( 0x01c41628, "MDCFG10 ata/cf" ); dumpreg( 0x01c4162c, "MDCFG11 vlynq" ); dumpreg( 0x01c41630, "MDCFG12 hpi" ); dumpreg( 0x01c41634, "MDCFG13 ddr2" ); dumpreg( 0x01c41638, "MDCFG14 emifa" ); dumpreg( 0x01c4163c, "MDCFG15 mmc/sd/sdio" ); dumpreg( 0x01c41640, "MDCFG16 --" ); dumpreg( 0x01c41644, "MDCFG17 asp" ); dumpreg( 0x01c41648, "MDCFG18 i2c" ); dumpreg( 0x01c4164c, "MDCFG19 uart0" ); dumpreg( 0x01c41650, "MDCFG20 uart1" ); dumpreg( 0x01c41654, "MDCFG21 uart2" ); dumpreg( 0x01c41658, "MDCFG22 spi" ); dumpreg( 0x01c4165c, "MDCFG23 pwm0" ); dumpreg( 0x01c41660, "MDCFG24 pwm1" ); dumpreg( 0x01c41664, "MDCFG25 pwm2" ); dumpreg( 0x01c41668, "MDCFG26 gpio" ); dumpreg( 0x01c4166c, "MDCFG27 timer0" ); dumpreg( 0x01c41670, "MDCFG28 timer1" ); dumpreg( 0x01c4169c, "MDCFG39 c64x+ cpu" ); dumpreg( 0x01c41680, "MDCFG40 vicp" ); dumpreg( 0x01c41800, "MDSTAT0" ); dumpreg( 0x01c41804, "MDSTAT1" ); dumpreg( 0x01c41808, "MDSTAT2" ); printf("....\n"); // FIXME - still incomplete } //----------------------------------------------------------------------- // dump system module //----------------------------------------------------------------------- void dump_sys(void) { printf("--- System Module ---------------------\n"); dumpreg( 0x01c40000, "PINMUX0" ); dumpreg( 0x01c40004, "PINMUX1" ); dumpreg( 0x01c40008, "DSPBOOTADDR" ); dumpreg( 0x01c4000C, "SUSPSRC" ); dumpreg( 0x01c40010, "INTGEN" ); dumpreg( 0x01c40014, "BOOTCFG" ); dumpreg( 0x01c40028, "JTAGID" ); dumpreg( 0x01c40030, "HPI_CTL" ); dumpreg( 0x01c40034, "USBPHY_CTL" ); dumpreg( 0x01c40038, "CHP_SHRTSW" ); dumpreg( 0x01c4003C, "MSTPRI0" ); dumpreg( 0x01c40040, "MSTPRI1" ); dumpreg( 0x01c40044, "BPSS_CLKCTL" ); dumpreg( 0x01c40048, "VDD3P3V_PWDN" ); dumpreg( 0x01c4004C, "DRVVTPER" ); } //----------------------------------------------------------------------- // dump VENC //----------------------------------------------------------------------- void dump_venc(void) { printf("--- VENC Registers ---------------------\n"); dumpreg( 0x01C72400, "VMOD" ); dumpreg( 0x01C72404, "VIDCTL" ); dumpreg( 0x01C72408, "VDPRO" ); dumpreg( 0x01C7240C, "SYNCCTL" ); dumpreg( 0x01C72410, "HSPLS" ); dumpreg( 0x01C72414, "VSPLS" ); dumpreg( 0x01C72418, "HINT" ); dumpreg( 0x01C7241C, "HSTART" ); dumpreg( 0x01C72420, "HVALID" ); dumpreg( 0x01C72424, "VINT" ); dumpreg( 0x01C72428, "VSTART" ); dumpreg( 0x01C7242C, "VVALID" ); dumpreg( 0x01C72430, "HSDLY" ); dumpreg( 0x01C72434, "VSDLY" ); dumpreg( 0x01C72438, "YCCCTL" ); dumpreg( 0x01C7243C, "RGBCTL" ); dumpreg( 0x01C72440, "RGBCLP" ); dumpreg( 0x01C72444, "LINECTL" ); dumpreg( 0x01C72448, "CULLLINE" ); dumpreg( 0x01C7244C, "LCDOUT" ); dumpreg( 0x01C72450, "BRTS" ); dumpreg( 0x01C72454, "BRTW" ); dumpreg( 0x01C72458, "ACCTL" ); dumpreg( 0x01C7245C, "PWMP" ); dumpreg( 0x01C72460, "PWMW" ); dumpreg( 0x01C72464, "DCLKCTL" ); dumpreg( 0x01C72468, "DCLKPTN0" ); dumpreg( 0x01C7246C, "DCLKPTN1" ); dumpreg( 0x01C72470, "DCLKPTN2" ); dumpreg( 0x01C72474, "DCLKPTN3" ); dumpreg( 0x01C72478, "DCLKPTN0A" ); dumpreg( 0x01C7247C, "DCLKPTN1A" ); dumpreg( 0x01C72480, "DCLKPTN2A" ); dumpreg( 0x01C72484, "DCLKPTN3A" ); dumpreg( 0x01C72488, "DCLKHS" ); dumpreg( 0x01C7248C, "DCLKHSA" ); dumpreg( 0x01C72490, "DCLKHR" ); dumpreg( 0x01C72494, "DCLKVS" ); dumpreg( 0x01C72498, "DCLKVR" ); dumpreg( 0x01C7249C, "CAPCTL" ); dumpreg( 0x01C724A0, "CAPDO" ); dumpreg( 0x01C724A4, "CAPDE" ); dumpreg( 0x01C724A8, "ATR0" ); dumpreg( 0x01C724AC, "ATR1" ); dumpreg( 0x01C724B0, "ATR2" ); dumpreg( 0x01C724B4, "STN_LCDCT" ); dumpreg( 0x01C724B8, "VSTAT" ); dumpreg( 0x01C724BC, "RAMADR" ); dumpreg( 0x01C724C0, "RAMPORT" ); dumpreg( 0x01C724C4, "DACTST" ); dumpreg( 0x01C724C8, "YCOLVL" ); dumpreg( 0x01C724CC, "SCPROG" ); //dumpreg( 0x01C724D0, "" ); //dumpreg( 0x01C724D4, "" ); //dumpreg( 0x01C724D8, "" ); dumpreg( 0x01C724DC, "CVBS" ); dumpreg( 0x01C724E0, "CMPNT" ); dumpreg( 0x01C724E4, "ETMG0" ); dumpreg( 0x01C724E8, "ETMG1" ); dumpreg( 0x01C724EC, "ETMG2" ); dumpreg( 0x01C724F0, "ETMG3" ); dumpreg( 0x01C724F4, "DACSEL" ); //dumpreg( 0x01C724F8, "" ); //dumpreg( 0x01C724FC, "" ); dumpreg( 0x01C72500, "ARGBX0" ); dumpreg( 0x01C72504, "ARGBX1" ); dumpreg( 0x01C72508, "ARGBX2" ); dumpreg( 0x01C7250C, "ARGBX3" ); dumpreg( 0x01C72510, "ARGBX4" ); dumpreg( 0x01C72514, "DRGBX0" ); dumpreg( 0x01C72518, "DRGBX1" ); dumpreg( 0x01C7251C, "DRGBX2" ); dumpreg( 0x01C72520, "DRGBX3" ); dumpreg( 0x01C72524, "DRGBX4" ); dumpreg( 0x01C72528, "VSTARTA" ); dumpreg( 0x01C7252C, "OSDCLK0" ); dumpreg( 0x01C72530, "OSDCLK1" ); dumpreg( 0x01C72534, "HVLDCL0" ); dumpreg( 0x01C72538, "HVLDCL1" ); dumpreg( 0x01C7253C, "OSDHAD" ); } //----------------------------------------------------------------------- // dump OSD //----------------------------------------------------------------------- void dump_osd(void) { printf("--- OSD Registers ----------------------\n"); dumpreg( 0x01C72600, "MODE" ); dumpreg( 0x01C72604, "VIDWINMD" ); dumpreg( 0x01C72608, "OSDWIN0MD" ); dumpreg( 0x01C7260C, "OSDWIN1MD" ); dumpreg( 0x01C72610, "OSDATRMD" ); dumpreg( 0x01C72614, "RECTCUR" ); dumpreg( 0x01C72618, "VIDWIN0OFST" ); dumpreg( 0x01C7261C, "VIDWIN1OFST" ); dumpreg( 0x01C72620, "OSDWIN0OFST" ); dumpreg( 0x01C72624, "OSDWIN1OFST" ); //dumpreg( 0x01C72628, "" ); dumpreg( 0x01C7262C, "VIDWIN0ADR" ); dumpreg( 0x01C72630, "VIDWIN1ADR" ); //dumpreg( 0x01C72634, "" ); dumpreg( 0x01C72638, "OSDWIN0ADR" ); dumpreg( 0x01C7263C, "OSDWIN1ADR" ); dumpreg( 0x01C72640, "BASEPX" ); dumpreg( 0x01C72644, "BASEPY" ); dumpreg( 0x01C72648, "VIDWIN0XP" ); dumpreg( 0x01C7264C, "VIDWIN0YP" ); dumpreg( 0x01C72650, "VIDWIN0XL" ); dumpreg( 0x01C72654, "VIDWIN0YL" ); dumpreg( 0x01C72658, "VIDWIN1XP" ); dumpreg( 0x01C7265C, "VIDWIN1YP" ); dumpreg( 0x01C72660, "VIDWIN1XL" ); dumpreg( 0x01C72664, "VIDWIN1YL" ); dumpreg( 0x01C72668, "OSDWIN0XP" ); dumpreg( 0x01C7266C, "OSDWIN0YP" ); dumpreg( 0x01C72670, "OSDWIN0XL" ); dumpreg( 0x01C72674, "OSDWIN0YL" ); dumpreg( 0x01C72678, "OSDWIN1XP" ); dumpreg( 0x01C7267C, "OSDWIN1YP" ); dumpreg( 0x01C72680, "OSDWIN1XL" ); dumpreg( 0x01C72684, "OSDWIN1YL" ); dumpreg( 0x01C72688, "CURXP" ); dumpreg( 0x01C7268C, "CURYP" ); dumpreg( 0x01C72690, "CURXL" ); dumpreg( 0x01C72694, "CURYL" ); //dumpreg( 0x01C72698, "" ); //dumpreg( 0x01C7269C, "" ); dumpreg( 0x01C726A0, "W0BMP01" ); dumpreg( 0x01C726A4, "W0BMP23" ); dumpreg( 0x01C726A8, "W0BMP45" ); dumpreg( 0x01C726AC, "W0BMP67" ); dumpreg( 0x01C726B0, "W0BMP89" ); dumpreg( 0x01C726B4, "W0BMPAB" ); dumpreg( 0x01C726B8, "W0BMPCD" ); dumpreg( 0x01C726BC, "W0BMPEF" ); dumpreg( 0x01C726C0, "W1BMP0" ); dumpreg( 0x01C726C4, "W1BMP2" ); dumpreg( 0x01C726C8, "W1BMP4" ); dumpreg( 0x01C726CC, "W1BMP6" ); dumpreg( 0x01C726D0, "W1BMP8" ); dumpreg( 0x01C726D4, "W1BMPA" ); dumpreg( 0x01C726D8, "W1BMPC" ); dumpreg( 0x01C726DC, "W1BMPE" ); dumpreg( 0x01C726E0, "TI_TES" ); //dumpreg( 0x01C726E4, "" ); dumpreg( 0x01C726E8, "MISCCT" ); dumpreg( 0x01C726EC, "CLUTRAMYC" ); dumpreg( 0x01C726F0, "CLUTRAMC" ); dumpreg( 0x01C726F4, "TRANSPVA" ); //dumpreg( 0x01C726F8, "" ); dumpreg( 0x01C726FC, "PPVWIN0AD" ); } //----------------------------------------------------------------------- // look up table: linking names to dumper functions & decriptions //----------------------------------------------------------------------- struct { const char *name; // command name void (*func)(void); // dumper function const char *help; // command description } functions [] = { // name function description { "ddr", dump_ddr, "DDR2 controller" }, { "dma", dump_dma, "EDMA controller" }, { "dmaparm", dump_dmaparm, "EDMA parameter RAM" }, { "pll", dump_pll, "Phase Locked Loops" }, { "pri", dump_pri, "Priorities" }, { "psc", dump_psc, "Power Supply Control" }, { "sys", dump_sys, "System module" }, { "venc", dump_venc, "VENC Registers"}, { "osd", dump_osd, "OSD Registers"}, }; #define nr_functions (sizeof(functions)/sizeof(functions[0])) //----------------------------------------------------------------------- // application //----------------------------------------------------------------------- int main(int argc, char *argv[]) { int arg, fun; int found = 0; for (arg=1; arg < argc; arg++) // for each argument { for (fun=0; fun < nr_functions; fun++) // compare functions { if (strcmp( argv[arg], functions[fun].name) == 0) // if match { functions[fun].func(); // let's have fun found = 1; // user understands me } } } if (!found) // if no valid args { printf("DaVinci processor register dumper V0.0.2\n"); // print help printf("use: %s \n", argv[0]); for (fun=0; fun < nr_functions; fun++) { printf(" %-10s (%s)\n", functions[fun].name, functions[fun].help); } } return 0; } //----------------------------------- eof -------------------------------