Matthias Welwarsky wrote:
are you sure the sleep and wakeup code has to be in TCM? As far as I
understood the DDR controller documentation, Self-Refresh state is
automatically exited on a memory request.
Yes, this is my understanding as well. However, I think TCM is easier
to program, see below.
Shouldn't it be enough to make
sure that the code from writing the SLRF bit up to the WFI is in I-Cache?
First, we have to distinguish the two parts in sleep.S.
davinci_idle_loop_suspend doesn't need to be in TCM/ICache at all. It
can run from SDRAM as well cause it doesn't switch SDRAM to self
refresh. It's there only for easier programming/file layout. But maybe
we should add a SLRF switch there as well? Would be a trade of of wake
up time vs. power saving.
Second, davinci_cpu_suspend has to run *not* from SDRAM, anywhere else
will be okay, cause it switches SDRAM to self refresh. Yes, it can be
TCM, Cache, or (if switch between NOR and SRAM on DVEVM could be done
by software and not by jumper) it could run in external SRAM as well.
So options are TCM or Cache. Talking about cache, I think I-Cache is
not sufficent, data (if there is some) for the code between SLRF and
WFI has to be in D-Cache as well (or you do some tricky programming so
that no data is used and all adresses/literals are encoded directly in
the assembly instructions. OMAP1 sleep code does something like this
to avoid literal pools).
If you like to run it from Cache, you have to ensure that Data and
Code is really in Cache, and that no other Cache lines are replaced
and potentially tried to write to SDRAM while running from Cache. I
think this is really tricky to achive, at least more than copy the
stuff to TCM. Or do you know an easy method to get stuff into Cache?
The only one I know is executing the code and loading data once and
then *hoping* its in Cache and not replaced executing it a second time.
And, additionally, please note the ToDo statement:
/* ToDo: Currently, we only switch SDRAM to self refresh here. To
* save even more power, we should gate input clocks to the
* memory controller module off. See TI document SPRUE22C
* section 2.15 "Power management" for more details.
*/
With this implemented the section between SLRF and WFI would (a)
become larger (and then even more tricky to get into cache) and (b)
then the memory controller won't come out of SLRF automatically.
Best regards
Dirk
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