Hi, I am working on a custom prototyping board of DM6446. It has 128 MB of DDR2 SDRAM(2 memory chips ELPIDA E5116AHSE). DDR2 is configured as 32 bit. I want to calculate the time consumed in DMA transfer between External memory(DDR2) and L1D SRAM. L1D(80KB) is configured partly cache and partly SRAM. L2(64KB) is configured as cache completely. I went through following documents to calculate approximate DMA transfer time.
1.. tms320dm6446.pdf (DM6446 datasheet) 2.. sprue19c.pdf (TMS320DM644x DMSoC Peripherals Overview) 3.. sprue23c.pdf (TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide) 4.. sprue22c.pdf (TMS320DM644x DMSoC DDR2 Memory Controller User's Guide) 5.. E0908E40.pdf (DDR2 SDRAM data sheet) I found in sprue22c.pdf(page 34) that DDR 2 memory controller operates at 133 MHz. I got an understanding that (133000000*2)read/write operation can take place in 1 second because in case of DDR2 read/write can happen in both rising and falling edges of the clock. It will also depend on whether I am accessing the same bank or read/write is bursty. I found in sprue23c.pdf that EDMA 3 system runs at DSP frequency divided by 3 i.e. 594 MHz/3 = 198 MHz. I got an understanding that EDMA Controller is responsible for configuring and assigning physical channel for DMA transfer. It doesn't affect the time consumed in 2D-to-1D/1D-to-2D/2D-to-2D DMA transfer of a chunk of data between DDR2 and L1D SRAM. Please correct me if I am wrong. I calculate on the average DMA transfer per second = (133000000*2)*4 bytes (because DDR2 data bus is 32 bit). Hence DMA transfer time for 1 byte = 1/((133000000*2)*4) second . Can anybody tell me whether I am calculating correctly ? I am trying to find some calculation which will generate realistic figures that matches closely with the profile data for DMA transfer. I will do profiling of DMA transfer in terms of DSP clocks using 64 bit Timer available on DM6446. Please help me in finding an approximate calculation of time consumed in DMA transfer between DDR2 and L1D SRAM. Thanks in advance, Sandip
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