David, > TOTAL : 8880 0000 (128M)
Better double-check your math. 0x0800_0000 = 128MB. What you have is actually 136MB. This explains why DSP Link will not load anything above address 0x8800_0000, i.e. there's no more memory! Brad > -----Original Message----- > From: [EMAIL PROTECTED] > [mailto:[EMAIL PROTECTED] On Behalf > Of [EMAIL PROTECTED] > Sent: Wednesday, March 19, 2008 4:40 PM > To: [EMAIL PROTECTED]; [email protected] > Subject: RE: Codec Engine 2.0.1 woes > > Sam: > > Sorry I didn't get back to you promptly... I'm CC'ing the list also. > > I've compiled some info that might help... some of which you've no doubtly > done, but it's here nonetheless. > > Our Target Board: > TMS320DM6441 + 128MB DDR2 running montavista 2.6.10 patchlevel pro-1536 > (supported patchlevel). > > Here's own current working memory map... > > Memory Map: > > Base : 8000 0000 > > Linux : 8000 0000 +0500 0000 (80M) > CMEM : 8500 0000 +0220 0000 (34M) > DDRALG : 8720 0000 +00D0 0000 (13M) > DDR2 : 87F0 0000 +0080 0000 (8M) > RESET : 8870 0000 +0000 0080 (128B) > DSPLINK: 887F FF80 +000F FF80 (1M - 128B) > TOTAL : 8880 0000 (128M) > > Some observations: > > 1. Setting DDR2 to 0x88000000 and above made dsplink fail to load for some > reason. > I've heard about silicon bugs that affect the VPSS's ability to access > frame buffers above those locations. > Maybe this had something to do with the fact that I also shrunk it from 8M > to 7M when I moved it, but it seems particular to where it's located. > > 2. Our CMEM is so big because, by default , eVRU soaks up a huge chunk for > best performance (can be scaled back all the way to 2M however). > > 3. I couldn't figure out how to lay out the memory map without a > DDRALGHEAP > section and pass it a CMEM alloc'd section using Engine_redefineHeap. > That would be the most flexible solution allow you to make different pools > to service alg heap depending on what is loaded... for now it's not worth > the effort! > > 4. I noticed your RESET section was 512 bytes... is this a function of the > chip variant you're using? > 128B seemed to work fine for me. > > Ok, now for the fun part of modifying the configs to actually get this to > work. > > I installed all tools in /opt/ti-tools because this seemed be the most > common prefix that I found. > Here's my versions list: > > CE 2.00.01 (default directory) > xdc 3.00.06 (default directory) > dspbios 5.32.01.05 (default directory) > c6000 code gen 6.0.16 (/opt/ti-tools/c6000/cgtools) > > After installing the above, I made my life a lot easier by making a whole > bunch of symlinks and then started hunting for redundant installs. > This makes configuring 3rd party packages nice because your symlink names > are stable while the TI install names are not. > > Links: > bios -> /opt/ti-tools/bios_5_32_01 > codec_engine -> /opt/ti-tools/codec_engine_2_00_01 > xdais-> /opt/codec_engine/cetools/packages/ti/xdais > xdctools -> xdc_3_00_06 > dsplink -> /opt/codec_engine/cetools/packages/dsplink > framework_components -> /opt/codec_engine/cetools/packages/ti/sdo/fc > > Redundant installs to kill: > bios/xdctools = delete and replace with symlink pointing to > /opt/ti-tools/xdctools > > Modifications Part 1: Platform Modifications > > Here's the diff of the platform modifications that I did for the xdc tools. > The clockRate change was for DM6441 clocks... you'll probably not want to > change those. > > Make the same changes for: > /bios_5_32_01/packages/ti/platforms/evmDM6446/Platform.tci > /bios_5_32_01/packages/ti/platforms/evmDM6446/Platform.xdc > > Index: > X:/linux/TI_DspTools/xdc_3_00_06/packages/ti/platforms/evmDM6446/Platfor m. > xdc > =================================================================== > --- > X:/linux/TI_DspTools/xdc_3_00_06/packages/ti/platforms/evmDM6446/Platfor m. > xdc > (revision 14) > +++ > X:/linux/TI_DspTools/xdc_3_00_06/packages/ti/platforms/evmDM6446/Platfor m. > xdc > (revision 15) > @@ -42,7 +42,7 @@ > > readonly config xdc.platform.IExeContext.Cpu DSP = { > id: "0", > - clockRate: 567.0, > + clockRate: 513.0, > catalogName: "ti.catalog.c6000", > deviceName: "TMS320CDM6446", > revision: "1.0", > @@ -50,7 +50,7 @@ > > readonly config xdc.platform.IExeContext.Cpu GPP = { > id: "1", > - clockRate: 300.0, > + clockRate: 297.0, > catalogName: "ti.catalog.c470", > deviceName: "TMS320CDM6446", > revision: "1.0", > @@ -59,7 +59,7 @@ > instance: > > override config xdc.platform.IPlatform.Memory > externalMemoryMap[string] = [ > - ["DDR2", {name: "DDR2", base: 0x80000000, len: 0x10000000}], > + ["DDR2", {name: "DDR2", base: 0x80000000, len: 0x08000000}], > ]; > > /* default segment for data sections */ > Index: > X:/linux/TI_DspTools/xdc_3_00_06/packages/ti/platforms/evmDM6446/Platfor m. > tci > =================================================================== > --- > X:/linux/TI_DspTools/xdc_3_00_06/packages/ti/platforms/evmDM6446/Platfor m. > tci > (revision 14) > +++ > X:/linux/TI_DspTools/xdc_3_00_06/packages/ti/platforms/evmDM6446/Platfor m. > tci > (revision 15) > @@ -25,10 +25,10 @@ > var mem_ext = []; > > mem_ext[0] = { > - comment: "256Mbytes of the DSP's off-chip memory", > + comment: "128 Mbytes of the DSP's off-chip memory", > name: "DDR2", > base: 0x80000000, > - len: 0x10000000, > + len: 0x08000000, > space: "code/data" > }; > > @@ -40,7 +40,7 @@ > }; > > var params = { > - clockRate: 567, > + clockRate: 513, > catalogName: "ti.catalog.c6000", > deviceName: "DM6446", > regs: device_regs, > > Modifications Part 2: DSPLINK config changes > > I ran the dsplink/config/bin/dsplinkcfg.pl file and enabled all objects by > listing every letter that was available in the config options. > > Here are my diffs for the memory map layout: > > Index: > X:/linux/TI_DspTools/codec_engine_2_00_01/cetools/packages/dsplink_orig/ co > nfig/all/CFG_Davinci.c > =================================================================== > --- > X:/linux/TI_DspTools/codec_engine_2_00_01/cetools/packages/dsplink_orig/ co > nfig/all/CFG_Davinci.c > (revision 19) > +++ > X:/linux/TI_DspTools/codec_engine_2_00_01/cetools/packages/dsplink_orig/ co > nfig/all/CFG_Davinci.c > (revision 20) > @@ -57,8 +57,8 @@ > FALSE, /* AUTOSTART : Autostart the DSP (Not > supported) */ > "DEFAULT.OUT", /* EXECUTABLE : Executable for > autostart */ > TRUE, /* DOPOWERCTRL : Link does the Power > Ctrl of DSP. */ > - 0x8FF00020, /* RESUMEADDR : Resume address */ > - 0x8FF00000, /* RESETVECTOR : Reset Vector for the > DSP */ > + 0x88700020, /* RESUMEADDR : Resume address */ > + 0x88700000, /* RESETVECTOR : Reset Vector for the > DSP */ > 0x80, /* RESETCODESIZE : Size of code at DSP > Reset Vector */ > 1, /* MADUSIZE : DSP Minimum > Addressable > Data Unit */ > Endianism_Little, /* ENDIAN : DSP Endianism */ > @@ -80,8 +80,8 @@ > { > 0, /* ENTRY : Entry number */ > "DSPLINKMEM", /* NAME : Name of the memory > region */ > - 0x8FE00000, /* ADDRPHYS : Physical address */ > - 0x8FE00000, /* ADDRDSPVIRT : DSP virtual address */ > + 0x88700080, /* ADDRPHYS : Physical address */ > + 0x88700080, /* ADDRDSPVIRT : DSP virtual address */ > (Uint32) -1, /* ADDRGPPVIRT : GPP virtual address > (if > known) */ > 0x5000, /* SIZE : Size of the memory > region */ > TRUE /* SHARED : Shared access memory? > */ > @@ -89,17 +89,17 @@ > { > 1, /* ENTRY : Entry number */ > "DSPLINKMEM1", /* NAME : Name of the memory > region */ > - 0x8FE05000, /* ADDRPHYS : Physical address */ > - 0x8FE05000, /* ADDRDSPVIRT : DSP virtual address */ > + 0x88705080, /* ADDRPHYS : Physical address */ > + 0x88705080, /* ADDRDSPVIRT : DSP virtual address */ > (Uint32) -1, /* ADDRGPPVIRT : GPP virtual address > (if > known) */ > - 0xFB000, /* SIZE : Size of the memory > region */ > + 0xFAF80, /* SIZE : Size of the memory > region */ > TRUE /* SHARED : Shared access memory? > */ > }, > { > 2, /* ENTRY : Entry number */ > "RESETCTRL", /* NAME : Name of the memory > region */ > - 0x8FF00000, /* ADDRPHYS : Physical address */ > - 0x8FF00000, /* ADDRDSPVIRT : DSP virtual address */ > + 0x88700000, /* ADDRPHYS : Physical address */ > + 0x88700000, /* ADDRDSPVIRT : DSP virtual address */ > (Uint32) -1, /* ADDRGPPVIRT : GPP virtual address > (if > known) */ > 0x00000080, /* SIZE : Size of the memory > region */ > FALSE /* SHARED : Shared access memory? > */ > @@ -107,10 +107,10 @@ > { > 3, /* ENTRY : Entry number */ > "DDR", /* NAME : Name of the memory > region */ > - 0x8FF00080, /* ADDRPHYS : Physical address */ > - 0x8FF00080, /* ADDRDSPVIRT : DSP virtual address */ > + 0x87F00000, /* ADDRPHYS : Physical address */ > + 0x87F00000, /* ADDRDSPVIRT : DSP virtual address */ > (Uint32) -1, /* ADDRGPPVIRT : GPP virtual address > (if > known) */ > - 0xFFF80, /* SIZE : Size of the memory > region */ > + 0x00800000, /* SIZE : Size of the memory > region */ > FALSE /* SHARED : Shared access memory? > */ > }, > { > Index: > X:/linux/TI_DspTools/codec_engine_2_00_01/cetools/packages/dsplink_orig/ ds > p/inc/DspBios/Davinci/dsplink-davinci-base.tci > =================================================================== > --- > X:/linux/TI_DspTools/codec_engine_2_00_01/cetools/packages/dsplink_orig/ ds > p/inc/DspBios/Davinci/dsplink-davinci-base.tci > (revision 19) > +++ > X:/linux/TI_DspTools/codec_engine_2_00_01/cetools/packages/dsplink_orig/ ds > p/inc/DspBios/Davinci/dsplink-davinci-base.tci > (revision 20) > @@ -23,7 +23,7 @@ > > > params = { > - clockRate: 450, > + clockRate: 513, > catalogName: "ti.catalog.c6000", > deviceName: "DM420", > }; > @@ -67,8 +67,8 @@ > * > ======================================================================== == > == > */ > var DSPLINKMEM = prog.module("MEM").create("DSPLINKMEM"); > -DSPLINKMEM.base = 0x8FE00000; > -DSPLINKMEM.len = 0x100000; > +DSPLINKMEM.base = 0x88700080; > +DSPLINKMEM.len = 0x000FFF80; > DSPLINKMEM.createHeap = false; > DSPLINKMEM.comment = "DSPLINKMEM"; > > @@ -77,7 +77,7 @@ > * > ======================================================================== == > == > */ > var RESET_VECTOR = prog.module("MEM").create("RESET_VECTOR"); > -RESET_VECTOR.base = 0x8FF00000; > +RESET_VECTOR.base = 0x88700000; > RESET_VECTOR.len = 0x00000080; > RESET_VECTOR.space = "code/data"; > RESET_VECTOR.createHeap = false; > @@ -88,8 +88,8 @@ > * > ======================================================================== == > == > */ > var DDR = prog.module("MEM").create("DDR"); > -DDR.base = 0x8FF00080; > -DDR.len = 0x000FFF80; > +DDR.base = 0x87F00000; > +DDR.len = 0x00800000; > DDR.space = "code/data"; > DDR.createHeap = true; > DDR.heapSize = 0x10000; > > I rebuilt dsplink and tested the samples which ran ok. > > Modifications Part 3: Codec Engine Server changes. > > Add: environment['xdc.cfg.check.fatal'] = 'false'; > To: codec_engine/examples/ti/sdo/ce/examples/servers/all_codec/all.cfg > To: > codec_engine/examples/ti/sdo/ce/examples/servers/video_copy/evmDM6446/vi de > o_copy.cfg > > Here's the diffs of configuration changes: > > Index: > X:/linux/TI_DspTools/codec_engine_2_00_01/examples/ti/sdo/ce/examples/se rv > ers/all_codecs/all.tcf > =================================================================== > --- > X:/linux/TI_DspTools/codec_engine_2_00_01/examples/ti/sdo/ce/examples/se rv > ers/all_codecs/all.tcf > (revision 22) > +++ > X:/linux/TI_DspTools/codec_engine_2_00_01/examples/ti/sdo/ce/examples/se rv > ers/all_codecs/all.tcf > (revision 23) > @@ -19,28 +19,28 @@ > { > comment: "DDRALGHEAP: off-chip memory for dynamic algmem > allocation", > name: "DDRALGHEAP", > - base: 0x88000000, // 128MB > - len: 0x07A00000, // 122MB > + base: 0x87200000, > + len: 0x00D00000, // 13M > space: "code/data" > }, > { > comment: "DDR2: off-chip memory for application code and data", > name: "DDR2", > - base: 0x8FA00000, // 250MB > - len: 0x00400000, // 4MB > + base: 0x87F00000, > + len: 0x00800000, // 8MB > space: "code/data" > }, > { > comment: "DSPLINK: off-chip memory reserved for DSPLINK code and > data", > name: "DSPLINKMEM", > - base: 0x8FE00000, // 254MB > - len: 0x00100000, // 1MB > + base: 0x87FFFF80, > + len: 0x000FFF80, // 1MB - 128B > space: "code/data" > }, > { > comment: "RESET_VECTOR: off-chip memory for the reset vector > table", > name: "RESET_VECTOR", > - base: 0x8FF00000, > + base: 0x88700000, > len: 0x00000080, > space: "code/data" > }, > @@ -99,7 +99,7 @@ > }; > > var params = { > - clockRate: 594, > + clockRate: 513, > catalogName: "ti.catalog.c6000", > deviceName: "DM6446", > regs: device_regs, > @@ -175,8 +175,8 @@ > * GBL > * > ======================================================================== == > = > */ > -/* set MAR register to cache external memory 0x80000000-0x8FFFFFFF */ > -prog.module("GBL").C64PLUSMAR128to159 = 0x0000ffff; > +/* set MAR register to cache external memory 0x80000000-0x87FFFFFF */ > +prog.module("GBL").C64PLUSMAR128to159 = 0x000000ff; > > prog.module("GBL").ENABLEALLTRC = false; > prog.module("GBL").PROCID = 0; > @@ -212,14 +212,14 @@ > * MEM : Global > * > ======================================================================== == > = > */ > -prog.module("MEM").BIOSOBJSEG = bios.DDR2; > -prog.module("MEM").MALLOCSEG = bios.DDR2; > +//prog.module("MEM").BIOSOBJSEG = bios.DDR2; > +//prog.module("MEM").MALLOCSEG = bios.DDR2; > > /* > ======================================================================== == > = > * TSK : Global > * > ======================================================================== == > = > */ > -prog.module("TSK").STACKSEG = bios.DDR2; > +//prog.module("TSK").STACKSEG = bios.DDR2; > > /* > ======================================================================== == > = > * Generate configuration files... > > > Modifications Part 4: Codec Engine App changes > > Index: > X:/linux/TI_DspTools/codec_engine_2_00_01/examples/ti/sdo/ce/examples/ap ps > /video_copy/dualcpu/evmDM6446/ceapp.cfg > =================================================================== > --- > X:/linux/TI_DspTools/codec_engine_2_00_01/examples/ti/sdo/ce/examples/ap ps > /video_copy/dualcpu/evmDM6446/ceapp.cfg > (revision 20) > +++ > X:/linux/TI_DspTools/codec_engine_2_00_01/examples/ti/sdo/ce/examples/ap ps > /video_copy/dualcpu/evmDM6446/ceapp.cfg > (revision 21) > @@ -53,15 +53,15 @@ > * // segments in the Server's BIOS configuration (.tcf) script. > * // There is exactly one "main", one "link", and one "reset" > * // segment type, and zero or more of "other" types. > - * myEngine.armDspLinkConfig = { > - * memTable: [ > - * ["DDRALGHEAP", {addr: 0x88000000, size: 0x07A00000, type: > "other"}], > - * ["DDR2", {addr: 0x8FA00000, size: 0x00400000, type: > "main" }], > - * ["DSPLINKMEM", {addr: 0x8FE00000, size: 0x00100000, type: > "link" }], > - * ["RESETCTRL", {addr: 0x8FF00000, size: 0x00000080, type: > "reset"}], > - * ], > - * }; > - */ > + */ > + myEngine.armDspLinkConfig = { > + memTable: [ > + ["DDRALGHEAP", {addr: 0x87200000, size: 0x00D00000, type: > "other"}], > + ["DDR2", {addr: 0x87F00000, size: 0x00800000, type: > "main" > }], > + ["DSPLINKMEM", {addr: 0x88700080, size: 0x000FFF80, type: > "link" > }], > + ["RESETCTRL", {addr: 0x88700000, size: 0x00000080, type: > "reset"}], > + ], > + }; > + environment['xdc.cfg.check.fatal'] = 'false'; > /* > * @(#) ti.sdo.ce.examples.apps.video_copy.dualcpu.evmDM6446; 1, 0, > 0,55; > 1-14-2008 09:51:44; /db/atree/library/trees/ce-g30x/src/ > */ > > > After all those changes were in place, I rebuilt CMEM for good measure and, > after tweaking all my xdcpaths, successfully built the video_copy app and > all the sever-side components. > Although I had success with running the video_copy program on the target > board, I couldn't get any of the apps that had local/remote configs to > work... no real skin off my back because I just needed to see anything > work > before moving to eVRU (which is working now by the way). > > Hope this helps out in getting CE 2.00.01 to work with 128MB... > > Regards, > > David > > DAVID A. KONDRAD > Software Design Engineer > On-Q/Legrand > www.onqlegrand.com > > _______________________________________________ > Davinci-linux-open-source mailing list > [email protected] > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
