The NAND chip does not use extended wait cycles on the EMIF, and
thus has no reason to care about setting the polarity of those wait
cycles. (SPRUE20B 2.5.6.7: The WP0 bit in the AWCCR does not affect
the NAND Flash status register).
I believe the polarity is also set incorrectly - all devices (NAND,
ATA, CF via the CPLD) on the DVEVM use EM_WAIT as active low. There
is actually an inconsistency in SPRUE20B - Table 4 says "WP0=1
selects active-low polarity", but then immediately below says "When
set to 1, the EMIF will wait if the EM_WAIT pin is high". Section
2.5.8 agrees with the second statement, as does Table 32. This
inconsistency is probably how the error came about. I've submitted
feedback to TI on this.
The reset value of this bit is actually 1 anyway, so this patch
alone should not break any devices which rely on this behaviour
(though I can't explain how they ever worked...).
Signed-off-by: Bernard Blackham <[EMAIL PROTECTED]>
---
drivers/mtd/nand/davinci_nand.c | 4 ----
1 file changed, 4 deletions(-)
Index: linux-2.6.24-tl1/drivers/mtd/nand/davinci_nand.c
===================================================================
--- linux-2.6.24-tl1.orig/drivers/mtd/nand/davinci_nand.c 2008-04-18
03:15:05.000000000 +0800
+++ linux-2.6.24-tl1/drivers/mtd/nand/davinci_nand.c 2008-04-18
03:15:09.000000000 +0800
@@ -435,10 +435,6 @@ static void __devinit nand_davinci_flash
"by bootloader.\n", regval, tmp);
}
- regval = davinci_nand_readl(AWCCR_OFFSET);
- regval |= 0x10000000;
- davinci_nand_writel(regval, AWCCR_OFFSET);
-
/*------------------------------------------------------------------*
* NAND FLASH CHIP TIMEOUT @ 459 MHz *
* *
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