Hi, Can anyone help me or can give some hints for solving my problem as described in the mail below? Thanks in advance. -mohit
--- On Thu, 15/5/08, Mohit Chauhan <[EMAIL PROTECTED]> wrote: > From: Mohit Chauhan <[EMAIL PROTECTED]> > Subject: Problem in using ACPY3 on DM6446 EVM under Codec engine > To: [email protected] > Date: Thursday, 15 May, 2008, 4:01 PM > Hi, > > We are facing a problem. My team is developing a video > decoder on C64x+ DSP of DM6446 EVM. The algorithm uses > ACPY3. The Algorithm with ACPY3 enabled, works well on > DM6446 simulator. Also it works under Codec Engine (CE) on > DM6437 DSK(where there is single DSP and no ARM). > > We are facing problem that when we disable ACPY3, we are > able to use decoder to decode the file on DM6446 EVM under > CE. but the system hangs when decoder with ACPY3 enabled is > run under CE on DM6446 EVM. From our debug prints, we come > to now that the decoder hangs when the call to the > VIDDEC_process function is made, where we use ACPY3 for the > first time. > > I am attaching the map and cfg file of the decoder server, > and the tcf file used for decoder server. > > Can anyone guide me what could be the reason. We are using > CE ver 1.02 on linux, and VICP is not being used. > > The relevant portion of the .map file is: > ****************************************************************************** > TMS320C6x COFF Linker Unix v6.0.3 > > ****************************************************************************** > >> Linked Thu May 15 14:07:03 2008 > > OUTPUT FILE NAME: <Mpeg4Dec_Server.x64P> > ENTRY POINT SYMBOL: "_c_int00" address: 8fa63d80 > > > MEMORY CONFIGURATION > > name origin length used > unused attr fill > ---------------------- -------- --------- -------- > -------- ---- -------- > ARM_RAM 10008000 00004000 00000000 > 00004000 RWIX > VICP 11100000 0001f400 00000000 > 0001f400 RWIX > CACHE_L2 11800000 00010000 00000000 > 00010000 RWIX > CACHE_L1P 11e08000 00008000 00000000 > 00008000 RWIX > L1DSRAM 11f04000 00010000 00008000 > 00008000 RWIX > CACHE_L1D 11f14000 00004000 00000000 > 00004000 RWIX > DDRALGHEAP 88000000 07a00000 07a00000 > 00000000 RWIX > DDR 8fa00000 00400000 0008296d > 0037d693 RWIX > DSPLINKMEM 8fe00000 00100000 00000000 > 00100000 RWIX > RESET_VECTOR 8ff00000 00000080 00000000 > 00000080 RWIX > > > The TCF file used for server is: > /* > * Setup platform-specific memory map: > */ > var mem_ext = [ > { > comment: "DDRALGHEAP: off-chip memory for > dynamic algmem allocation", > name: "DDRALGHEAP", > base: 0x88000000, // 128MB > len: 0x07A00000, // 122MB > space: "code/data" > }, > { > comment: "DDR: off-chip memory for application > code and data", > name: "DDR", > base: 0x8FA00000, // 250MB > len: 0x00400000, // 4MB > space: "code/data" > }, > { > comment: "DSPLINK: off-chip memory reserved for > DSPLINK code and data", > name: "DSPLINKMEM", > base: 0x8FE00000, // 254MB > len: 0x00100000, // 1MB > space: "code/data" > }, > { > comment: "RESET_VECTOR: off-chip memory for the > reset vector table", > name: "RESET_VECTOR", > base: 0x8FF00000, > len: 0x00000080, > space: "code/data" > }, > ]; > > > /* > * Internal memory partitioning > * > * On the left in the diagram below is the layout of > internal memory > * available on DM6446 for data caching and as RAM; on the > right is the > * diagram showing how this configuration file partitions > the available > * 64k+80k of memory. (The 32K for program cache is not > affected by this > * configuration.) Please find more specifics on how the > configuration is > * done further below. > * > * > * Physical internal memory on DM6446 Default > partitioning in this .tcf > * > * |//////////| > |//////////| > * 0x11800000 +----------+ 0x11800000 > +----------+ > * | L2Cache | | > | > * | and/or | 64k | L2 > Cache | 64k > * | IRAM | | > | > * | | | > | > * 0x11810000 +----------+ 0x11810000 > +----------+ > * |//////////| > |//////////| > * : : : > : > * |//////////| > |//////////| > * 0x11F04000 +----------+ 0x11F04000 > +----------+ > * | | | > | > * | L1DSRAM | 48k | > L1DSRAM | > * | | | > | 64k > * 0x11F10000 +- - - - - + | > | > * |L1Cache or| 32k +- - > - - - + > * |more L1DSR| 0x11F14000 | L1 > cache | 16k > * 0x11F18000 +----------+ 0x11F18000 > +----------+ > * |//////////| > |//////////| > */ > > > /* > * Specify the L2 CACHE memory setting. This value > indicates how the physical > * internal memory of size 64K starting at 0x11800000 will > be split between > * L2 cache and a general-purpose internal memory segment > IRAM. The options > * are: > * l2Mode: "0k" -- IRAM is 64K long, starts at > 0x11800000; no L2 cache > * l2Mode: "32k" -- IRAM is 32K long, starts at > 0x11800000; L2 cache is > * 32K long, starts at 0x11808000 > * l2Mode: "64k" -- no IRAM; L2 cache is 64k > long, starts at 0x11800000 > */ > var device_regs = { > l2Mode: "64k" > }; > > var params = { > clockRate: 567, > catalogName: "ti.catalog.c6000", > deviceName: "DM6446", > regs: device_regs, > mem: mem_ext > }; > > /* > * Customize generic platform with parameters specified > above. > */ > utils.loadPlatform("ti.platforms.generic", > params); > > /* > =========================================================================== > * Enable heaps and tasks > * > =========================================================================== > */ > bios.enableMemoryHeaps(prog); > bios.enableTskManager(prog); > > /* > =========================================================================== > * Configure L1 cache and L1DSRAM segment > * > * In addition to the 64K at address 0x11800000, the > DM6446 device has another > * 48K of physical memory at 0x11F04000 available as > internal RAM, > * called the "L1DSRAM" segment in BIOS, and it > has another adjacent 32K > * at 0x11F10000 that can either be used entirely for L1 > cache, > * or split between L1 cache and more internal memory. > * > * The 80K segment (48K + 32K) starts at 0x11F04000. When > powered on, the > * device uses the upper 32K for L1 cache entirely, so > BIOS by default defines > * the L1DSRAM segment to be 48K long and does not change > the cache. > * > * We can change the default behavior, by shrinking the L1 > cache and adding > * the extra space to L1DSRAM. We can set the L1 cache to > be 32K (the default) > * or 16K, 8K, 4K, or 0K. The corresponding L1DSRAM sizes > then are 48K (the > * default), or 64K, 72K, 76K, or 80K. > * > * The L1DSRAM segment always starts at 0x11F04000. > * > =========================================================================== > */ > prog.module("GBL").C64PLUSCONFIGURE = true; > prog.module("GBL").C64PLUSL1DCFG = > "16k"; // changed from default of 32k > > /* increase the size of the L1DSRAM by 16K because L1 > Cache size has been > * reduced by 16K > */ > bios.L1DSRAM.len += 0x4000; > > > /* > =========================================================================== > * Create heaps in memory segments that are to have heap > * > =========================================================================== > */ > bios.DDR.createHeap = true; > bios.DDR.heapSize = 0x20000; // 512K > > bios.DDRALGHEAP.createHeap = true; > bios.DDRALGHEAP.heapSize = bios.DDRALGHEAP.len; > > bios.L1DSRAM.createHeap = true; > bios.L1DSRAM.enableHeapLabel = true; > bios.L1DSRAM["heapLabel"] = > prog.extern("L1DHEAP"); > bios.L1DSRAM.heapSize = 0x8000; > > > /* > =========================================================================== > * GBL > * > =========================================================================== > */ > /* set MAR register to cache external memory > 0x80000000-0x8FFFFFFF */ > prog.module("GBL").C64PLUSMAR128to159 = > 0x0000ffff; > > prog.module("GBL").ENABLEALLTRC = false; > prog.module("GBL").PROCID = 0; > > /* user init function calls Link's HAL initialization > */ > prog.module("GBL").CALLUSERINITFXN = 1; > prog.module("GBL").USERINITFXN = > prog.extern("HAL_init"); > > > /* > =========================================================================== > * Enable cpu load measurement TODO: this should be in > OSAL!!! > * > =========================================================================== > */ > var cpuLoad = > prog.module("IDL").create("Global_cpuLoad"); > cpuLoad.fxn = prog.extern("LOAD_idlefxn"); > cpuLoad.calibration = true; > > /* > =========================================================================== > * MEM : startup and SWI stack size > * > =========================================================================== > */ > prog.module("MEM").STACKSIZE = 0x1000; > > /* > =========================================================================== > * Global Settings > * > =========================================================================== > */ > prog.module("MEM").ARGSSIZE = 256; > > /* > =========================================================================== > * Enable MSGQ and POOL Managers > * > =========================================================================== > */ > bios.MSGQ.ENABLEMSGQ = true; > bios.POOL.ENABLEPOOL = true; > > /* > =========================================================================== > * Set all code and data sections to use DDR > * > =========================================================================== > */ > bios.setMemCodeSections (prog, bios.DDR); > bios.setMemDataNoHeapSections (prog, bios.DDR); > bios.setMemDataHeapSections (prog, bios.DDR); > > /* > =========================================================================== > * MEM : Global > * > =========================================================================== > */ > prog.module("MEM").BIOSOBJSEG = bios.DDR; > prog.module("MEM").MALLOCSEG = bios.DDR; > > /* > =========================================================================== > * TSK : Global > * > =========================================================================== > */ > prog.module("TSK").STACKSEG = bios.DDR; > > /* > =========================================================================== > * Generate configuration files... > * > =========================================================================== > */ > if (config.hasReportedError == false) { > prog.gen(); > } > > > > > The server's cfg file is: > function _cfg(prog, verbose) { > > /* initialize prog attrs from build model */ > var build = { > releases: { > > $name:"xdc.bld.Executable.Instance#0/attrs/releases", > }, > target: { > $name:"ti.targets.C64P", > module$meta$init: {}, > instance$meta$init: {}, > instance$init: {}, > module$static$init: {}, > instance$static$init: {}, > name: "C64P", > suffix: "64P", > isa: "64P", > model: { > $name:"ti.targets.C64P/model", > endian: "little" > }, > rts: "ti.targets.rts6000", > base: { > $name:"ti.targets.C62", > module$meta$init: {}, > instance$meta$init: {}, > instance$init: {}, > module$static$init: {}, > instance$static$init: {}, > name: "C62", > suffix: "62", > isa: "62", > model: { > $name:"ti.targets.C62/model", > endian: "little" > }, > rts: "ti.targets.rts6000", > platform: > "ti.platforms.sim6xxx%3ATMS320C6211", > platforms: { > > $name:"ti.targets.C62/platforms", > }, > debugGen: { > > $name:"ti.targets.C62/debugGen", > execTemplate: > "ti/targets/ccs_exec.xdt", > execPattern: > "%24%28cfgDir%29%24%28cfgName%29.pjt", > packageTemplate: > "ti/targets/ccs_package.xdt", > packagePattern: > "package/%24%28pkgName%29.pjt" > }, > extensions: { > > $name:"ti.targets.C62/extensions", > ".s62": { > > $name:"ti.targets.C62/extensions/'.s62'", > suf: ".s62", > typ: "asm" > }, > ".asm": { > > $name:"ti.targets.C62/extensions/'.asm'", > suf: ".asm", > typ: "asm" > }, > ".c": { > > $name:"ti.targets.C62/extensions/'.c'", > suf: ".c", > typ: "c" > }, > ".cpp": { > > $name:"ti.targets.C62/extensions/'.cpp'", > suf: ".cpp", > typ: "cpp" > }, > ".cxx": { > > $name:"ti.targets.C62/extensions/'.cxx'", > suf: ".cxx", > typ: "cpp" > }, > ".C": { > > $name:"ti.targets.C62/extensions/'.C'", > suf: ".C", > typ: "cpp" > }, > ".cc": { > > $name:"ti.targets.C62/extensions/'.cc'", > suf: ".cc", > typ: "cpp" > } > }, > versionMap: { > > $name:"ti.targets.C62/versionMap", > "TMS320C6x_4.32": > "1%2C0%2C4.32%2C0", > "TMS320C55x_2.56": > "1%2C0%2C2.56%2C0", > "TMS320C54x_3.83": > "1%2C0%2C3.83%2C0", > "TMS320C2000_3.07": > "1%2C0%2C3.07%2C0" > }, > profiles: { > > $name:"ti.targets.C62/profiles", > debug: { > > $name:"ti.targets.C62/profiles/'debug'", > compileOpts: { > > $name:"ti.targets.C62/profiles/'debug'/compileOpts", > copts: "-g", > defs: "-D_DEBUG_%3D1" > } > }, > release: { > > $name:"ti.targets.C62/profiles/'release'", > compileOpts: { > > $name:"ti.targets.C62/profiles/'release'/compileOpts", > copts: "-o2" > } > }, > profile: { > > $name:"ti.targets.C62/profiles/'profile'", > compileOpts: { > > $name:"ti.targets.C62/profiles/'profile'/compileOpts", > copts: "-gp" > } > }, > coverage: { > > $name:"ti.targets.C62/profiles/'coverage'", > compileOpts: { > > $name:"ti.targets.C62/profiles/'coverage'/compileOpts", > copts: "-gp" > } > }, > alchemy: { > > $name:"ti.targets.C62/profiles/'alchemy'", > compileOpts: { > > $name:"ti.targets.C62/profiles/'alchemy'/compileOpts", > } > } > }, > sectMap: { > > $name:"ti.targets.C62/sectMap", > ".text": "code", > ".stack": "data", > ".bss": "data", > ".cinit": "data", > ".pinit": "data", > ".const": "data", > ".data": "data", > ".switch": "data", > ".sysmem": "data", > ".far": "data", > ".args": "data", > ".cio": "data", > ".vecs": "code" > }, > stdTypes: { > > $name:"ti.targets.C62/stdTypes", > t_Arg: { > > $name:"ti.targets.C62/stdTypes/t_Arg", > size: 4, > align: 4 > }, > t_Char: { > > $name:"ti.targets.C62/stdTypes/t_Char", > size: 1, > align: 1 > }, > t_Double: { > > $name:"ti.targets.C62/stdTypes/t_Double", > size: 8, > align: 8 > }, > t_Float: { > > $name:"ti.targets.C62/stdTypes/t_Float", > size: 4, > align: 4 > }, > t_Fxn: { > > $name:"ti.targets.C62/stdTypes/t_Fxn", > size: 4, > align: 4 > }, > t_Int: { > > $name:"ti.targets.C62/stdTypes/t_Int", > size: 4, > align: 4 > }, > t_Int8: { > > $name:"ti.targets.C62/stdTypes/t_Int8", > size: 1, > align: 1 > }, > t_Int16: { > > $name:"ti.targets.C62/stdTypes/t_Int16", > size: 2, > align: 2 > }, > t_Int32: { > > $name:"ti.targets.C62/stdTypes/t_Int32", > size: 4, > align: 4 > }, > t_Int40: { > > $name:"ti.targets.C62/stdTypes/t_Int40", > size: 8, > align: 8 > }, > t_Int64: { > > $name:"ti.targets.C62/stdTypes/t_Int64", > size: 8, > align: 8 > }, > t_Long: { > > $name:"ti.targets.C62/stdTypes/t_Long", > size: 8, > align: 8 > }, > t_LDouble: { > > $name:"ti.targets.C62/stdTypes/t_LDouble", > size: 8, > align: 8 > }, > t_LLong: { > > $name:"ti.targets.C62/stdTypes/t_LLong", > size: 8, > align: 8 > }, > t_Ptr: { > > $name:"ti.targets.C62/stdTypes/t_Ptr", > size: 4, > align: 4 > }, > t_Short: { > > $name:"ti.targets.C62/stdTypes/t_Short", > size: 2, > align: 2 > } > }, > scompile: {}, > getVersion: {}, > getISAChain: {} > }, > platform: "ti.platforms.evmDM6446", > platforms: { > > $name:"ti.targets.C64P/platforms", > }, > version: > "ti.targets.C64P%7B1%2C0%2C6.0%2C3", > debugGen: { > $name:"ti.targets.C64P/debugGen", > execTemplate: > "ti/targets/ccs_exec.xdt", > execPattern: > "%24%28cfgDir%29%24%28cfgName%29.pjt", > packageTemplate: > "ti/targets/ccs_package.xdt", > packagePattern: > "package/%24%28pkgName%29.pjt" > }, > extensions: { > > $name:"ti.targets.C64P/extensions", > ".s64P": { > > $name:"ti.targets.C64P/extensions/'.s64P'", > suf: ".s64P", > typ: "asm" > }, > ".s64": { > > $name:"ti.targets.C64P/extensions/'.s64'", > suf: ".s64", > typ: "asm" > }, > ".s62": { > > $name:"ti.targets.C64P/extensions/'.s62'", > suf: ".s62", > typ: "asm" > }, > ".asm": { > > $name:"ti.targets.C64P/extensions/'.asm'", > suf: ".asm", > typ: "asm" > }, > ".c": { > > $name:"ti.targets.C64P/extensions/'.c'", > suf: ".c", > typ: "c" > }, > ".cpp": { > > $name:"ti.targets.C64P/extensions/'.cpp'", > suf: ".cpp", > typ: "cpp" > }, > ".cxx": { > > $name:"ti.targets.C64P/extensions/'.cxx'", > suf: ".cxx", > typ: "cpp" > }, > ".C": { > > $name:"ti.targets.C64P/extensions/'.C'", > suf: ".C", > typ: "cpp" > }, > ".cc": { > > $name:"ti.targets.C64P/extensions/'.cc'", > suf: ".cc", > typ: "cpp" > } > }, > versionMap: { > > $name:"ti.targets.C64P/versionMap", > "TMS320C6x_4.32": > "1%2C0%2C4.32%2C0", > "TMS320C55x_2.56": > "1%2C0%2C2.56%2C0", > "TMS320C54x_3.83": > "1%2C0%2C3.83%2C0", > "TMS320C2000_3.07": > "1%2C0%2C3.07%2C0" > }, > rootDir: > "/home/mohit/dvevm_1_10/cg6x_6_0_3", > profiles: { > $name:"ti.targets.C64P/profiles", > debug: { > > $name:"ti.targets.C64P/profiles/'debug'", > compileOpts: { > > $name:"ti.targets.C64P/profiles/'debug'/compileOpts", > copts: "-g", > defs: "-D_DEBUG_%3D1" > } > }, > release: { > > $name:"ti.targets.C64P/profiles/'release'", > compileOpts: { > > $name:"ti.targets.C64P/profiles/'release'/compileOpts", > copts: "-o2" > } > }, > profile: { > > $name:"ti.targets.C64P/profiles/'profile'", > compileOpts: { > > $name:"ti.targets.C64P/profiles/'profile'/compileOpts", > copts: "-gp" > } > }, > coverage: { > > $name:"ti.targets.C64P/profiles/'coverage'", > compileOpts: { > > $name:"ti.targets.C64P/profiles/'coverage'/compileOpts", > copts: "-gp" > } > }, > alchemy: { > > $name:"ti.targets.C64P/profiles/'alchemy'", > compileOpts: { > > $name:"ti.targets.C64P/profiles/'alchemy'/compileOpts", > } > } > }, > sectMap: { > $name:"ti.targets.C64P/sectMap", > ".text": "code", > ".stack": "data", > ".bss": "data", > ".cinit": "data", > ".pinit": "data", > ".const": "data", > ".data": "data", > ".switch": "data", > ".sysmem": "data", > ".far": "data", > ".args": "data", > ".cio": "data", > ".vecs": "code" > }, > stdTypes: { > $name:"ti.targets.C64P/stdTypes", > t_Arg: { > > $name:"ti.targets.C64P/stdTypes/t_Arg", > size: 4, > align: 4 > }, > t_Char: { > > $name:"ti.targets.C64P/stdTypes/t_Char", > size: 1, > align: 1 > }, > t_Double: { > > $name:"ti.targets.C64P/stdTypes/t_Double", > size: 8, > align: 8 > }, > t_Float: { > > $name:"ti.targets.C64P/stdTypes/t_Float", > size: 4, > align: 4 > }, > t_Fxn: { > > $name:"ti.targets.C64P/stdTypes/t_Fxn", > size: 4, > align: 4 > }, > t_Int: { > > $name:"ti.targets.C64P/stdTypes/t_Int", > size: 4, > align: 4 > }, > t_Int8: { > > $name:"ti.targets.C64P/stdTypes/t_Int8", > size: 1, > align: 1 > }, > t_Int16: { > > $name:"ti.targets.C64P/stdTypes/t_Int16", > size: 2, > align: 2 > }, > t_Int32: { > > $name:"ti.targets.C64P/stdTypes/t_Int32", > size: 4, > align: 4 > }, > t_Int40: { > > $name:"ti.targets.C64P/stdTypes/t_Int40", > size: 8, > align: 8 > }, > t_Int64: { > > $name:"ti.targets.C64P/stdTypes/t_Int64", > size: 8, > align: 8 > }, > t_Long: { > > $name:"ti.targets.C64P/stdTypes/t_Long", > size: 8, > align: 8 > }, > t_LDouble: { > > $name:"ti.targets.C64P/stdTypes/t_LDouble", > size: 8, > align: 8 > }, > t_LLong: { > > $name:"ti.targets.C64P/stdTypes/t_LLong", > size: 8, > align: 8 > }, > t_Ptr: { > > $name:"ti.targets.C64P/stdTypes/t_Ptr", > size: 4, > align: 4 > }, > t_Short: { > > $name:"ti.targets.C64P/stdTypes/t_Short", > size: 2, > align: 2 > } > }, > scompile: {}, > getVersion: {}, > getISAChain: {} > }, > test: { > > $name:"xdc.bld.Executable.Instance#0/attrs/test", > }, > cfgScript: "Mpeg4Dec_Server.tcf", > profile: "debug", > lopts: "-l%20link.cmd", > defs: > "%20-Dxdc_cfg__xheader__%3D%27%3Cservers/Mpeg4Dec_Server/package/cfg/Mpeg4Dec_Server_x64P.h%3E%27%20%20-Dxdc_cfg__xheader__%3D%27%3Cservers/Mpeg4Dec_Server/package/cfg/Mpeg4Dec_Server_x64P.h%3E%27%20%20-Dxdc_cfg__xheader__%3D%27%3Cservers/Mpeg4Dec_Server/package/cfg/Mpeg4Dec_Server_x64P.h%3E%27%20" > }; > _runescape(build); > build.cfgArgs = undefined; > prog.build = build; > prog.name = 'Mpeg4Dec_Server.x64P'; > prog.endian = prog.build.target.model.endian; > > /* use the platform package's Platform module */ > var Platform = > xdc.useModule('ti.platforms.evmDM6446.Platform'); > prog.platformName = 'ti.platforms.evmDM6446'; > var platCfg = {}; > _runescape(platCfg); > prog.platform = Platform.create('', platCfg); > > /* record the executable's package name */ > prog.$$bind('$buildpkg', > 'servers.Mpeg4Dec_Server'); > prog.$$bind('$$isasm', 0); > > /* bind prog to an appropriate execution context */ > prog.cpu = prog.platform.getExeContext(prog); > > /* import the target's run-time support pkg */ > xdc.loadPackage('ti.targets.rts6000'); > > /* import the executable's package */ > var home = > xdc.loadPackage('servers.Mpeg4Dec_Server'); > xdc.om.$$bind('$homepkg', home); > var spath = '.'; > > /* load & run program cfg script and monitor all > loaded files */ > _runCfg('Mpeg4Dec_Server.tcf', spath, > 'package/cfg/Mpeg4Dec_Server_x64P', true, true, > platCfg); > var cout = null; > > /* get the exec command for this executable */ > if (prog.execCmd == null) { > prog.execCmd = prog.platform.getExecCmd(prog, > xdc.om['ti.platforms.evmDM6446'].packageBase); > } > var cout = 'define EXEC.' + prog.name + > '\n\n'; > cout += prog.execCmd; > cout += '\nendef\n\n'; > > utils.genDep('package/cfg/Mpeg4Dec_Server_x64P', > 'servers.Mpeg4Dec_Server', utils.loadedFiles, > cout,'package/cfg/Mpeg4Dec_Server_x64Pcfg.s62 > package/cfg/Mpeg4Dec_Server_x64Pcfg_c.c'); > > /* define function to run user's config file */ > function _runCfg(cfgScript, path, programName, > legacyTcf, legacyCfg, platParams) { > if (legacyTcf) { > var $save = {prog:utils.global.prog, > Program:Program}; > environment["config.programName"] = > programName; > environment["config.platform"] = > Program.platformName; > utils.seedPath = > environment["config.importPath"]; > utils.loadPlatform.params = platParams; > Program = $$legacy.Program; > utils.importFile(cfgScript, path); > $$legacy.prog = utils.global.prog; > utils.global.prog = $save.prog; > Program = $save.Program; > if (legacyCfg) { > > utils.importFile(cfgScript.replace(/\.tcf/, > ".cfg"), path); > } > } else { > utils.importFile(cfgScript, path); > } > } > > /* define function to decode _serialized strings */ > function _runescape(obj) { > for (var i in obj) { > if (obj[i] != null) { > if (typeof obj[i] == "string") { > obj[i] = unescape(obj[i]); > } else { > if (typeof obj[i] == > "object") { > _runescape(obj[i]); > } > } > } > } > } > > } > > /* run configuration script */ > _cfg(xdc.om['xdc.cfg.Program'], false); > > > Regards, > Mohit _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
