Hi,
I wonder if anyone has a similar problem. For the past year, we have been
using the Davinci TMX320 DM6443BZWT dye on our costum board with u-boot 1.1.3,
dvdsk 1.10, Linux 2.6.20 GIT and everything seems to run fine. Recently, we
switched over to the lower-power-consumption TMS320DM6441ZWT dye using the
exact same u-boot, kernel and dvdsk software and have been experiencing
occasional Davinci system lockup/crash problems, in which everything just stops
(power still seems good but all the interfaces are dead and don't respond); I
have to do a power-up reset to recover. With the new dye, I can get the
Davinci to crash by running an application on the ARM side that continuously
samples the mic (AIC33 codec), gives the data to the DSP via the CE API to
encode, gives the encoded data to the DSP to decode, and then playing the
decoded data to the speaker (AIC33 codec); sometimes it happens within an hour,
sometimes several hours. With the old dye, I
can run this for hours without crashing.
I wonder if we have to use any new recent u-boot or DVDSK or Linux kernel
software that is more compatible with the new Davinci dyes. When it crashes, I
don't get any kernel panic or other error messages, the whole system just halt
without any warnings. The old and new dyes we're using are both Silicon
Revision 1.3. I went through the errata
(davinci_tms320dm6441_errata-revG-apr-2008.pdf) between the different silicon
revisions and wondered if it could be related Advisory 1.1.6 (see below). Our
Davinci system is using 336Mhz for the DSP, 168Mhz for the ARM, (336/3) or
112Mhz for VCLK, and 132Mhz for MCLK. If anyone can provide any insight into
this or have experienced this, I would appreciate if you can share your
resolution to this problem. Thanks in advance.
Regards,
Andy
Advisory 1.1.6 DDR2: Multiple Master Access to the DDR2 at the Same Time may
Cause Master to
Stop
Revision(s) Affected: 1.1
Details: If multiple masters (CPUs or master peripherals) are accessing the
DDR2 Memory
Controller simultaneously and at least one of the masters is performing 64-byte
burst
transfers to the DDR2 Memory Controller, one of the masters may stop, requiring
a
power-up reset to recover.
Workaround: Reliable operation is achieved when the DDR2 Memory Controller VCLK
and MCLK are
set to a 1:1 ratio. The lockup is sensitive to non 1:1 frequency ratios between
the clock
used by the DDR2 Memory Controller (VCLK) and the clock used by the DDR2 PHY
interface to the external bus (MCLK).
For more detailed information on the clocks to the DDR2 Memory Controller, see
the
TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (literature number
SPRUE22).
The recommended clock configurations are:
DSP CPU clock at 486 MHz
ARM CPU clock at 243 MHz
VCLK at 162 MHz
MCLK at 162 MHz
DSP CPU clock at 567 MHz
ARM CPU clock at 283.5 MHz
VCLK at 189 MHz
MCLK at 189 MHz
Note: A DDR2 clock rate of 189 MHz is only supported on silicon revision 1.1 as
a
workaround for this advisory. For silicon revisions 1.2 and later, see the
device-specific
data manual for the DDR maximum clock rate supported.
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