Hi,
i have read the "DSP two-level internal memory reference guide (spru610)" &
"DSP cache user guide (spru656)" but
still have some questions about the dm6446 DSP side's cache:
1. by reading these two guides, it seems that level-1 memory ( L1D, L1P) are
always used as cache and level-2 can be configured as
SRAM or cache. but i found that on the dm6446 memory map described in
sprs283 and .tcf file when using DSP/BIOS, there
is a memory region named L1D RAM ranged from 0x11f04000 ~ 0x11f0ffff and
another named L1D RAM/cache ranged from
0x11f10000 ~ 0x11f17fff. does it mean L1D can also be configured as RAM
or cache? how? any restriction?
2. when using DSP/BIOS on dm6446, does it defaultly set all L2 memory as
SRAM (64K) and L1D and L1P as caches? should i enable the caches
in run-time? and what are the default cacheability setting of L2SRAM and
DDR(external memory)?
thanks in advance.
best,
kashin lin
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