Hi. It looks like your arm must boot dsp at start, but dsplinks power control module is switched off. Try to switch on this, pasting the following string in your arm-application .cfg file: <myEngine>.armDspLinkConfig.doPowerControl = true;
<myEngine> - name of your engine, witch you define in same place like var myEngine = Engine.createFromServer(...) or var myEngine = Engine.create(..) On Thu, 2008-06-12 at 17:15 +0300, Agat-system tut by wrote: > Hello , > > Here is description of the problem: > > We are using eInfochip DVPB board with DM6446 ans software: > > - Monta Vista Linux > - Codec Engine 2.10 > - DSPLINK 1.50 > - DSP/BIOS 5.32.01 > > We have downloaded application report SPRAAH9A “Motion JPEG Demo on > TMS320DM6446” from ti.com and corresponding source code. > > First of all we got dsp\jpegencdecCombo.x64P from sources. > But after EngineOpen call, application generates next error: > > DSP-side configuration mismatch/failure > 0 -> success > Positive value -> DSP-side failure code. > (Uint32) -1 -> DSP-side component was not initialized. > > DRV configuration status [0xffffffff] > IPS configuration status [0xffffffff] > POOL configuration status [0xffffffff] > MPCS configuration status [0xffffffff] > MPLIST configuration status [0xffffffff] > MQT configuration status [0xffffffff] > RINGIO configuration status [0xffffffff] > > Then we decided to assemble our server from codecs in the source package -- > dsp\jpegdec and dsp\jpegenc. > As result – after EngineOpen call we get errors that are logged in log2.txt > (attached). Memory map was carefully verified. > .cfg server file is also attached. > > > -- > Best regards, > Agat-system mailto:[EMAIL PROTECTED] > _______________________________________________ Davinci-linux-open-source > mailing list [email protected] > http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
