Description:
Adds the clock related changes for dm6467.
Signed-off-by: Sudhakar Rajashekhara <[EMAIL PROTECTED]>
---
arch/arm/mach-davinci/clock.c | 73 +++++++++++++++++++++++++++++++--
include/asm-arm/arch-davinci/timex.h | 15 ++++++-
2 files changed, 82 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 4826fcf..1d3735b 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -26,11 +26,17 @@
/* PLL/Reset register offsets */
#define PLLM 0x110
+/* Oscillation Frequency */
+#define OSC_FREQ 27000000 /* 27 MHZ */
+
static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex);
static DEFINE_SPINLOCK(clockfw_lock);
static unsigned int commonrate;
+static unsigned int div_by_four;
+static unsigned int div_by_six;
+static unsigned int div_by_eight;
static unsigned int armrate;
static unsigned int fixedrate = 27000000; /* 27 MHZ */
@@ -247,6 +253,45 @@ static struct clk davinci_clks[] = {
.usecount = 1,
}
};
+static struct clk davinci_dm6467_clks[] = {
+ {
+ .name = "ARMCLK",
+ .rate = &armrate,
+ .lpsc = -1,
+ .flags = ALWAYS_ENABLED,
+ },
+ {
+ .name = "UART0",
+ .rate = &fixedrate,
+ .lpsc = DAVINCI_DM646X_LPSC_UART0,
+ },
+ {
+ .name = "UART1",
+ .rate = &fixedrate,
+ .lpsc = DAVINCI_DM646X_LPSC_UART1,
+ },
+ {
+ .name = "UART2",
+ .rate = &fixedrate,
+ .lpsc = DAVINCI_DM646X_LPSC_UART2,
+ },
+ {
+ .name = "I2CCLK",
+ .rate = &div_by_four,
+ .lpsc = DAVINCI_DM646X_LPSC_I2C,
+ },
+ {
+ .name = "gpio",
+ .rate = &commonrate,
+ .lpsc = DAVINCI_DM646X_LPSC_GPIO,
+ },
+ {
+ .name = "AEMIFCLK",
+ .rate = &div_by_four,
+ .lpsc = DAVINCI_DM646X_LPSC_AEMIF,
+ .usecount = 1,
+ },
+};
#ifdef CONFIG_DAVINCI_RESET_CLOCKS
/*
@@ -275,15 +320,33 @@ late_initcall(clk_disable_unused);
int __init davinci_clk_init(void)
{
struct clk *clkp;
- int count = 0;
+ static struct clk *board_clks;
+ int count = 0, num_clks;
u32 pll_mult;
pll_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM);
- commonrate = ((pll_mult + 1) * 27000000) / 6;
- armrate = ((pll_mult + 1) * 27000000) / 2;
+ commonrate = ((pll_mult + 1) * OSC_FREQ) / 6;
+ armrate = ((pll_mult + 1) * OSC_FREQ) / 2;
+
+ if (cpu_is_davinci_dm6467()) {
+ fixedrate = 24000000;
+ div_by_four = ((pll_mult + 1) * OSC_FREQ) / 4;
+ div_by_six = ((pll_mult + 1) * OSC_FREQ) / 6;
+ div_by_eight = ((pll_mult + 1) * OSC_FREQ) / 8;
+ armrate = ((pll_mult + 1) * OSC_FREQ) / 2;
+
+ board_clks = davinci_dm6467_clks;
+ num_clks = ARRAY_SIZE(davinci_dm6467_clks);
+ } else {
+ fixedrate = OSC_FREQ;
+ armrate = (pll_mult + 1) * (fixedrate / 2);
+ commonrate = armrate / 3;
+
+ board_clks = davinci_clks;
+ num_clks = ARRAY_SIZE(davinci_clks);
+ }
- for (clkp = davinci_clks; count < ARRAY_SIZE(davinci_clks);
- count++, clkp++) {
+ for (clkp = board_clks; count < num_clks; count++, clkp++) {
clk_register(clkp);
/* Turn on clocks that have been enabled in the
diff --git a/include/asm-arm/arch-davinci/timex.h
b/include/asm-arm/arch-davinci/timex.h
index e4ec97f..1f69259 100644
--- a/include/asm-arm/arch-davinci/timex.h
+++ b/include/asm-arm/arch-davinci/timex.h
@@ -11,7 +11,20 @@
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
+#include <asm/arch/cpu.h>
+
/* The source frequency for the timers is the 27MHz clock */
-#define CLOCK_TICK_RATE 27000000
+#ifdef CONFIG_MACH_DAVINCI_EVM
+#define CLOCK_TICK_RATE 24000000
+#else
+#define CLOCK_TICK_RATE 148500000
+#endif
+#define DM644X_CLOCK_TICK_RATE 27000000
+#define DM646X_CLOCK_TICK_RATE 148500000
+#define DM355_CLOCK_TICK_RATE 24000000
+
+#define DAVINCI_CLOCK_TICK_RATE ((cpu_is_davinci_dm6467()) ? \
+ DM646X_CLOCK_TICK_RATE : ((cpu_is_davinci_dm644x()) ? \
+ DM644X_CLOCK_TICK_RATE : DM355_CLOCK_TICK_RATE))
#endif /* __ASM_ARCH_TIMEX_H__ */
--
1.5.4.1
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