Hi, we would like to use the CCD controller of the DM6446 as a fast data input interface (data width: 16 bit, not necessarily video/image data). Therefore we wrote a Linux driver, which allows to configure the CCDC and then captures the data into buffers in DDR2 memory, which are mapped with mmap to userspace.
Since we do not use any functions of the video processor (Preview Engine, Resizer...), we set SYN_MODE.WEN to 1, to make sure that the data is immediately stored to DDR2. The ISR of the driver is triggered by VDINT0, which is configured to be thrown at the last horizontal sync pulse of each data frame. The ISR also signals to the userspace, when a buffer is ready and could be read from DDR2. But unfortunately the VDINT0 interrupt (as well as the PCR.BUSY bit) does not indicate, when a frame is completely stored into DDR2 memory (by the EDMA engine). So while basically functioning very well, the driver frequently marks a buffer as "ready", when it is not :-(... Question is, if there is any hardware condition which indicates the time at which the data is completely stored in memory (when using the "SYN_MODE.WEN=1 output port" into DDR2 memory). Any ideas for circumventing this problem in another way are welcome too! Many thanks in advance and best regards, Kai _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
