Dear Brad:
I have changed some registers set basing on your set, and now, the
VGA video can be displayed on the monitor. But it seems some sets
are not suitable, the video is overlapped. I have changed some
registers value, but there is no changes. Would you please give me
some advice?
I use DM355 EVM board, and the set in below:
.name = VID_ENC_STD_1080I_30,
.std = 1,
.if_type = VID_ENC_IF_YCC16, /* TBD */
.interlaced = 0,
.xres = 640,
.yres = 480,
.fps = {60, 1},
.left_margin = 85,
.right_margin = 70,
.upper_margin = 32,
.lower_margin = 11,
.hsync_len = 9,
.vsync_len = 9,
.flags = 0,
the ths8200 registers set is below:
{THS8200_CHIP_CTL, 0xC1}, // chip_ctl
{THS8200_CSC_OFFS3, 0x03}, // csc_offset3
{THS8200_DATA_CNTL, 0x03}, // dman_cntl
{THS8200_DTG1_TOT_PIXELS_MSB, 0x03}, // dtg_total_pixel_msb
{THS8200_DTG1_TOT_PIXELS_LSB, 0x1b}, // dtg_total_pixel_lsb
{THS8200_DTG1_FLD_FLIP_LINECNT_MSB, 0x0}, // dtg_linecnt_msb
{THS8200_DTG1_LINECNT_LSB, 0x01}, // dtg_linecnt_lsb
{THS8200_DTG1_MODE, 0x87}, // dtg_mode
{THS8200_DTG1_FRAME_FIELD_SZ_MSB, 0x22}, //
dtg_frame_field_msb
{THS8200_DTG1_FRAME_SZ_LSB, 0x0c}, // dtg_frame_size_lsb
{THS8200_DTG1_FIELD_SZ_LSB, 0x0c}, // dtg_field_size_lsb
{THS8200_DTG1_VESA_CBAR_SIZE, 0x80}, // dtg_vesa_cbar_size
{THS8200_CSM_GY_CNTL_MULT_MSB, 0x8c}, //
{THS8200_CSM_MULT_BCB_RCR_MSB, 0x44},
{THS8200_CSM_MULT_RCR_BCB_CNTL, 0xc0}, // csm_mode
{THS8200_DTG2_HLENGTH_LSB, 0x9}, // dtg_hlength_lsb
{THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x0}, // dtg_hdly_msb
{THS8200_DTG2_HLENGTH_HDLY_LSB, 0x1}, // dtg_hdly_lsb
{THS8200_DTG2_VLENGTH1_LSB, 0x09}, // dtg_vlength_lsb
{THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x00}, // dtg_vdly_msb
{THS8200_DTG2_VDLY1_LSB, 0x01}, // dtg_vdly_lsb
{THS8200_DTG2_VLENGTH2_LSB, 0x00}, // dtg_vlength2_lsb
{THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07}, // dtg_vdly2_msb
{THS8200_DTG2_VDLY2_LSB, 0xFF}, // dtg_vdly2_lsb
{THS8200_DTG2_HS_IN_DLY_MSB, 0x00}, // dtg_hs_in_dly_msb
{THS8200_DTG2_HS_IN_DLY_LSB, 0x3c}, // dtg_hs_in_dly_lsb
{THS8200_DTG2_VS_IN_DLY_MSB, 0x00}, // dtg_vs_in_dly_msb
{THS8200_DTG2_VS_IN_DLY_LSB, 0x05}, // dtg_vs_in_dly_lsb
{THS8200_DTG2_CNTL, 0x43}, // pol_cntl
{0, 0},
Lori Gao
R&D center(Shanghai)
Rayco (Shanghai) Medical Products Company Limited
Carestream Health Inc.
Brad Bitterman <[EMAIL PROTECTED]>
11/26/2008 01:38 AM
To
Lori Gao <[EMAIL PROTECTED]>
cc
Subject
Re: about the ths8200 register set
These are the setting for 640x480 at 60HZ.
//THS8200
WR_REG,THS8200,0x01,0x03,0xC1 // chip_ctl
WR_REG,THS8200,0x01,0x19,0x03 // csc_offset3
WR_REG,THS8200,0x01,0x1C,0x70 // dman_cntl
WR_REG,THS8200,0x01,0x34,0x03 // dtg_total_pixel_msb
WR_REG,THS8200,0x01,0x35,0x20 // dtg_total_pixel_lsb
WR_REG,THS8200,0x01,0x36,0x80 // dtg_linecnt_msb
WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb
WR_REG,THS8200,0x01,0x38,0x87 // dtg_mode
WR_REG,THS8200,0x01,0x39,0x22 // dtg_frame_field_msb
WR_REG,THS8200,0x01,0x3A,0x0D // dtg_frame_size_lsb
WR_REG,THS8200,0x01,0x3B,0x0D // dtg_field_size_lsb
WR_REG,THS8200,0x01,0x3C,0x80 // dtg_vesa_cbar_size
WR_REG,THS8200,0x01,0x4A,0x8C // csm_mult_gy_msb
WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
WR_REG,THS8200,0x01,0x4C,0x00 // csm_mult_gy_lsb
WR_REG,THS8200,0x01,0x4D,0x00 // csm_mult_bcb_lsb
WR_REG,THS8200,0x01,0x4E,0x00 // csm_mult_rcr_lsb
WR_REG,THS8200,0x01,0x4F,0xC0 // csm_mode
WR_REG,THS8200,0x01,0x70,0x60 // dtg_hlength_lsb
WR_REG,THS8200,0x01,0x71,0x00 // dtg_hdly_msb
WR_REG,THS8200,0x01,0x72,0x01 // dtg_hdly_lsb
WR_REG,THS8200,0x01,0x73,0x03 // dtg_vlength_lsb
WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb
WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb
WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb
WR_REG,THS8200,0x01,0x77,0x07 // dtg_vdly2_msb
WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb
WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb
WR_REG,THS8200,0x01,0x7A,0x00 // dtg_hs_in_dly_lsb
WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb
WR_REG,THS8200,0x01,0x7C,0x00 // dtg_vs_in_dly_lsb
WR_REG,THS8200,0x01,0x82,0x43 // pol_cntl
You need to check the setup in the linux vpbe driver to match front
and back porch, pixel clock, HSync and VSync frequency.
- Brad
On Nov 25, 2008, at 2:20 AM, Lori Gao wrote:
Dear Bitterman :
I am using the ths8200 to output VGA signals, and now, i can see the
video in the monitor, but the position and quality is quite worse. I
have tried some set of the registers, but it seemed no use. Would
you please share your register set of ths8200?
The resolution of my output is 640 480
Best Regards!
Lori Gao
R&D center(Shanghai)
Rayco (Shanghai) Medical Products Company Limited
Carestream Health Inc.
