hi all:
The following are on the DM355 DEEP SLEEP code, how power is not, I do
not know how to deal with,
I would like to thank!
/* * linux/arch/arm/mach-davinci/sleep.S * * Assembly sleep routines for
DaVinci * * Copyright 2007 Dirk Behme <[EMAIL PROTECTED]> * * Based on
arch/arm/mach-omap2/sleep.S from: * * (C) Copyright 2004 * Texas Instruments,
<www.ti.com> * Richard Woodruff <[EMAIL PROTECTED]> * * (C) Copyright 2006
Nokia Corporation * Fixed idle loop sleep * Igor Stoppa <[EMAIL PROTECTED]> * *
This program is free software; you can redistribute it and/or * modify it under
the terms of the GNU General Public License as * published by the Free Software
Foundation; either version 2 of * the License, or (at your option) any later
version. * * This program is distributed in the hope that it will be useful, *
but WITHOUT ANY WARRANTY; without even the implied warranty of *
MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the * GNU General
Public License for more details. * * You should have received a copy of the GNU
General Public License * along with this program; if not, write to the Free
Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA
02111-1307 USA */
#include <linux/linkage.h>#include <asm/assembler.h>#include
<asm/arch/io.h>#include <asm/arch/hardware.h>
.text/* * davinci_cpu_suspend() - Forces DaVinci into sleep state by
switching * SDRAM into self refresh and then enter WFI.
*/ENTRY(davinci_cpu_suspend) stmfd sp!, {r4 - r12, lr}
/* tci_loop: mrc p15, 0, r15, c7, c10, 3 @ test clean
and invalidate DCache bne tci_loop mov r0, #0x0
@ clear for mrc call mcr p15, 0, r0, c7, c10, 4 @ drain write
buffer, @ hope SDR/DDR finished nop
nop */ bl Enter_SDRAM_Selfrefresh bl
Video_Dac_Down //bl PLL2_PLLDIV1_DOWN //bl
PSC_DOWN //bl PLL2_PLLCTL_DOWN //bl
PLL1_PLLCTL_DOWN //bl usb_phy_down //bl ddr_phy_down
bl deepsleep //bl ddr_phy_up //bl usb_phy_up
//bl PLL2_PLLCTL_UP //bl PLL1_PLLCTL_UP //bl
PSC_UP //bl PLL2_PLLDIV1_UP bl Video_Dac_Up
bl Exit_SDRAM_Selfrefresh ldmfd sp!, {r4 - r12, pc}
@ restore regs and return
SDRCR_ADDR: .word DDR2_CTRL_VIRT+0x0C SDRCR_LPMODEN_MASK: .word
0x80000000SDRCR_MCLKSTOPEN_MASK: .word 0x40000000SDRCR_SR_PD_MASK: .word
0x00800000 Enter_SDRAM_Selfrefresh: /* Switch SDRAM to
selfrefresh */ ldr r0, SDRCR_ADDR ldr r2, [r0] ldr
r1, SDRCR_SR_PD_MASK bic r2, r2, r1 ldr r1,
SDRCR_MCLKSTOPEN_MASK orr r2, r2, r1 ldr r1, SDRCR_LPMODEN_MASK
orr r2, r2, r1 str r2, [r0] /* ToDo: Wait T_CKE+1
cycles */ mov r1, #0x1000loop1: subs r1, r1, #0x1
bne loop1 mov pc, lr Exit_SDRAM_Selfrefresh: /* Exit
SDRAM selfrefresh */ ldr r0, SDRCR_ADDR ldr r2, [r0] ldr
r1, SDRCR_SR_PD_MASK orr r2, r2, r1 ldr r1, SDRCR_LPMODEN_MASK
bic r2, r2, r1 str r2, [r0] /* ToDo: Wait
T_SXNR+1 and/or T_SCRD+1 cylces */ mov r1, #0x1000loop2:
subs r1, r1, #0x1 bne loop2 mov pc, lr
SYS_MODULE_BASE =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE)SYS_MODULE_BASE_ADR: .word
SYS_MODULE_BASE
@@@ Video DACSYS_VPSS_CLK_CTRL_OFFSET = 0x44SYS_VPSS_CLK_CTRL_DACCLKEN =
0x10SYS_VPSS_CLK_CTRL_VENCLKEN = 0x8
SYS_VDAC_CONFIG_OFFSET = 0x2cSYS_VDAC_CONFIG_PWD_BGZ =
0x400SYS_VDAC_CONFIG_PWD_VBUFZ = 0x80
SYS_VTP_CONFIG_OFFSET=0x70SYS_VTP_CTRL_PWDSAVE =0x100SYS_VTP_CTRL_PWDRND
=0x40Video_Dac_Down: ldr r1, SYS_MODULE_BASE_ADR /* Video DAC clock,
VPBE/Video Encoder clock */ ldr r0, [r1, #SYS_VPSS_CLK_CTRL_OFFSET] bic
r0, r0, #SYS_VPSS_CLK_CTRL_DACCLKEN | SYS_VPSS_CLK_CTRL_VENCLKEN str r0,
[r1, #SYS_VPSS_CLK_CTRL_OFFSET] /* Video DAC config */ ldr r0, [r1,
#SYS_VDAC_CONFIG_OFFSET] bic r0, r0, #SYS_VDAC_CONFIG_PWD_BGZ |
SYS_VDAC_CONFIG_PWD_VBUFZ str r0, [r1, #SYS_VDAC_CONFIG_OFFSET] /* VTP
config */ ldr r0, [r1, #SYS_VTP_CONFIG_OFFSET] orr r0, r0,
#SYS_VTP_CTRL_PWDSAVE | SYS_VTP_CTRL_PWDRND str r0, [r1,
#SYS_VTP_CONFIG_OFFSET] mov pc, lr
Video_Dac_Up: ldr r1, SYS_MODULE_BASE_ADR /* Video DAC clock,
VPBE/Video Encoder clock */ ldr r0, [r1, #SYS_VPSS_CLK_CTRL_OFFSET] orr
r0, r0, #SYS_VPSS_CLK_CTRL_DACCLKEN | SYS_VPSS_CLK_CTRL_VENCLKEN str r0,
[r1, #SYS_VPSS_CLK_CTRL_OFFSET] /* Video DAC config */ ldr r0, [r1,
#SYS_VDAC_CONFIG_OFFSET] orr r0, r0, #SYS_VDAC_CONFIG_PWD_BGZ |
SYS_VDAC_CONFIG_PWD_VBUFZ str r0, [r1, #SYS_VDAC_CONFIG_OFFSET] /* VTP
config */ ldr r0, [r1, #SYS_VTP_CONFIG_OFFSET] bic r0, r0,
#SYS_VTP_CTRL_PWDSAVE | SYS_VTP_CTRL_PWDRND str r0, [r1,
#SYS_VTP_CONFIG_OFFSET] mov pc, lr@@@DDR PHYDDR_PHY_ADD :.word
DDR2_CTRL_VIRT+0xE4DDR_PHY_DLLPWRDN=0x50ddr_phy_down: ldr r1, DDR_PHY_ADD
ldr r0, [r1] orr r0, r0, #DDR_PHY_DLLPWRDN str r0, [r1] mov
pc, lr
ddr_phy_up: ldr r1, DDR_PHY_ADD ldr r0, [r1] bic r0, r0,
#DDR_PHY_DLLPWRDN str r0, [r1] mov pc, lr
@@@USB_PHY_CTRLSYS_USB_PHY_CONFIG_OFFSET=0x34SYS_USB_PHY_CTRL_PHYPDWN=0x1SYS_USB_PHY_CTRL_OTGPDWN=0x2SYS_USB_PHY_CTRL_VPSS_OSCPDWN=0x4
usb_phy_down: /* USB config */ ldr r1, SYS_MODULE_BASE_ADR
ldr r0, [r1, #SYS_USB_PHY_CONFIG_OFFSET] orr r0, r0,
#SYS_USB_PHY_CTRL_PHYPDWN |
SYS_USB_PHY_CTRL_OTGPDWN|SYS_USB_PHY_CTRL_VPSS_OSCPDWN str r0, [r1,
#SYS_USB_PHY_CONFIG_OFFSET] mov pc, lr
usb_phy_up: /* USB config */ ldr r1, SYS_MODULE_BASE_ADR ldr
r0, [r1, #SYS_USB_PHY_CONFIG_OFFSET] bic r0, r0,
#SYS_USB_PHY_CTRL_PHYPDWN |
SYS_USB_PHY_CTRL_OTGPDWN|SYS_USB_PHY_CTRL_VPSS_OSCPDWN str r0, [r1,
#SYS_USB_PHY_CONFIG_OFFSET]
mov pc, lr
@@@PLL1_PLLCTLPLL1_BASE = IO_ADDRESS(0x01C40800)PLL1_PLLCTL_ADD:.word
PLL1_BASEPLL1_PLLCTL_OFFSET=0x100PLL1_PLLCTL_AND=0x1PLL1_PLLCTL_OR =0x1A
PLL1_PLLCTL_DOWN: /* PLL1_PLLCTL config */ ldr r1,
PLL1_PLLCTL_ADD ldr r0, [r1, #PLL1_PLLCTL_OFFSET] bic r0,
r0, #PLL1_PLLCTL_AND str r0, [r1, #PLL1_PLLCTL_OFFSET]
orr r0, r0, #PLL1_PLLCTL_OR str r0, [r1, #PLL1_PLLCTL_OFFSET]
mov pc, lr
PLL1_PLLCTL_UP: /* PLL1_PLLCTL config */ ldr r1,
PLL1_PLLCTL_ADD ldr r0, [r1, #PLL1_PLLCTL_OFFSET] bic r0,
r0, #PLL1_PLLCTL_OR str r0, [r1, #PLL1_PLLCTL_OFFSET]
orr r0, r0, #PLL1_PLLCTL_AND str r0, [r1, #PLL1_PLLCTL_OFFSET]
mov pc, lr
@@@PLL2_PLLCTLPLL2_BASE = IO_ADDRESS(0x01C40C00)PLL2_PLLCTL_ADD: .word
PLL2_BASEPLL2_PLLCTL_OFFSET=0x100PLL2_PLLCTL_AND=0x1PLL2_PLLCTL_OR =0x1A
PLL2_PLLDIV1_OFFSET=0x118PLL2_PLLDIV1_CLEAR=0x8000PLL2_PLLDIV1_SET =0x8000
PLL2_PLLDIV1_DOWN: /* PLL2_PLLDIV1 config */ ldr r1,
PLL2_PLLCTL_ADD ldr r0, [r1, #PLL2_PLLDIV1_OFFSET] bic
r0, r0, #PLL2_PLLDIV1_CLEAR str r0, [r1, #PLL2_PLLDIV1_OFFSET]
mov pc, lr
PLL2_PLLDIV1_UP: /* PLL2_PLLDIV1 config */ ldr r1,
PLL2_PLLCTL_ADD ldr r0, [r1, #PLL2_PLLDIV1_OFFSET] orr
r0, r0, #PLL2_PLLDIV1_SET str r0, [r1, #PLL2_PLLDIV1_OFFSET]
mov pc, lr
PLL2_PLLCTL_DOWN: /* PLL2_PLLCTL config */ ldr r1,
PLL2_PLLCTL_ADD ldr r0, [r1, #PLL2_PLLCTL_OFFSET] bic r0,
r0, #PLL2_PLLCTL_AND str r0, [r1, #PLL2_PLLCTL_OFFSET]
orr r0, r0, #PLL2_PLLCTL_OR str r0, [r1, #PLL2_PLLCTL_OFFSET]
mov pc, lr
PLL2_PLLCTL_UP: /* PLL2_PLLCTL config */ ldr r1,
PLL2_PLLCTL_ADD ldr r0, [r1, #PLL2_PLLCTL_OFFSET] bic r0,
r0, #PLL2_PLLCTL_OR str r0, [r1, #PLL2_PLLCTL_OFFSET]
orr r0, r0, #PLL2_PLLCTL_AND str r0, [r1, #PLL2_PLLCTL_OFFSET]
mov pc, lr@@@PSCPSC_BASE =IO_ADDRESS(0x01C41000)PSC_ADD :.word
[EMAIL PROTECTED]
=0x2PSC_PTCMD_OFFSET=0x120PSC_PTCMD_AND=0x00;PSC_PTCMD_OR=0x1PSC_DOWN:
/* PSC config */ ldr r1, PSC_ADD ldr r0, [r1,
#PSC_MDCTL_OFFSET] bic r0, r0, #PSC_MDCTL_DDR_AND orr r0,
r0, #PSC_MDCTL_DDR_OR str r0, [r1, #PSC_MDCTL_OFFSET]
ldr r0, [r1, #PSC_PTCMD_OFFSET] bic r0, r0,
#PSC_PTCMD_AND orr r0, r0, #PSC_PTCMD_OR str r0, [r1,
#PSC_PTCMD_OFFSET]
mov pc, lr
PSC_UP: /* PSC config */ ldr r1, PSC_ADD ldr r0,
[r1, #PSC_MDCTL_OFFSET] bic r0, r0, #PSC_MDCTL_DDR_OR orr
r0, r0, #PSC_MDCTL_DDR_AND str r0, [r1, #PSC_MDCTL_OFFSET]
mov pc, lr
@@@ DeepSleepSYS_DEEPSLEEP_OFFSET = 0x48SYS_DEEPSLEEP_ENABLE_MASK =
0x80000000SYS_DEEPSLEEP_COMPLETE_MASK = 0x40000000deepsleep: ldr r2,
SYS_MODULE_BASE_ADR ldr r0, [r2, #SYS_DEEPSLEEP_OFFSET] orr r0,
r0, #SYS_DEEPSLEEP_ENABLE_MASK bic r0, r0, #SYS_DEEPSLEEP_COMPLETE_MASK
str r0, [r2, #SYS_DEEPSLEEP_OFFSET] mov r1, #0sleep_complete:
add r1, r1, #1 ldr r0, [r2, #SYS_DEEPSLEEP_OFFSET] @ load the deep
sleep reg tst r0, #SYS_DEEPSLEEP_COMPLETE_MASK @ test if the complete
bit is set beq sleep_complete @ if it's not 1,
keep waitingbreak_sleep: bic r0, r0,
#SYS_DEEPSLEEP_ENABLE_MASK|SYS_DEEPSLEEP_COMPLETE_MASK @ clear the enable bit
str r0, [r2, #SYS_DEEPSLEEP_OFFSET] mov pc, lr
ENTRY(davinci_cpu_suspend_sz) .word . - davinci_cpu_suspend
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